| /linux-6.14.4/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/ |
| D | dml2_mcg_dcn4.c | 54 if (soc_bb->clk_table.fclk.num_clk_values == 2) { in build_min_clk_table_fine_grained()
59 min_fclk_khz = soc_bb->clk_table.fclk.clk_values_khz[0]; in build_min_clk_table_fine_grained()
61 // First calculate the table for "balanced" bandwidths across UCLK/FCLK in build_min_clk_table_fine_grained()
69 …ble, effectively shift "up" all the dcfclk/fclk entries by 1, and then replace the lowest entry wi… in build_min_clk_table_fine_grained()
76 …am_bw_table.entries[i].min_fclk_khz, soc_bb->clk_table.fclk.clk_values_khz, soc_bb->clk_table.fclk… in build_min_clk_table_fine_grained()
108 min_table->dram_bw_table.entries[i].min_fclk_khz > min_table->max_clocks_khz.fclk) { in build_min_clk_table_fine_grained()
140 min_table->dram_bw_table.entries[i].min_fclk_khz = soc_bb->clk_table.fclk.clk_values_khz[i]; in build_min_clk_table_coarse_grained()
155 if (soc_bb->clk_table.dcfclk.num_clk_values < 2 || soc_bb->clk_table.fclk.num_clk_values < 2) in build_min_clock_table()
165 if (soc_bb->clk_table.fclk.num_clk_values == 2) { in build_min_clock_table()
169 if (soc_bb->clk_table.fclk.num_clk_values == soc_bb->clk_table.dcfclk.num_clk_values && in build_min_clock_table()
[all …]
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| /linux-6.14.4/Documentation/devicetree/bindings/clock/ |
| D | amlogic,c3-peripherals-clkc.yaml | 29 - description: input fclk div 2
30 - description: input fclk div 2p5
31 - description: input fclk div 3
32 - description: input fclk div 4
33 - description: input fclk div 5
34 - description: input fclk div 7
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| /linux-6.14.4/drivers/usb/host/ |
| D | ehci-sh.c | 13 struct clk *iclk, *fclk; member
114 priv->fclk = devm_clk_get(&pdev->dev, "usb_fck"); in ehci_hcd_sh_probe()
115 if (IS_ERR(priv->fclk)) in ehci_hcd_sh_probe()
116 priv->fclk = NULL; in ehci_hcd_sh_probe()
122 ret = clk_enable(priv->fclk); in ehci_hcd_sh_probe()
144 clk_disable(priv->fclk); in ehci_hcd_sh_probe()
162 clk_disable(priv->fclk); in ehci_hcd_sh_remove()
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| /linux-6.14.4/Documentation/devicetree/bindings/display/ti/ |
| D | ti,omap4-dss.txt | 14 - clocks: handle to fclk
36 - clocks: handle to fclk
51 - clocks: handles to fclk and iclk
67 - clocks: handle to fclk
88 - clocks: handles to fclk and pll clock
111 - clocks: handles to fclk and pll clock
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| D | ti,omap3-dss.txt | 14 - clocks: handle to fclk
37 - clocks: handle to fclk
52 - clocks: handles to fclk and iclk
64 - clocks: handle to fclk
82 - clocks: handles to fclk and pll clock
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| D | ti,omap5-dss.txt | 14 - clocks: handle to fclk
36 - clocks: handle to fclk
51 - clocks: handles to fclk and iclk
69 - clocks: handles to fclk and pll clock
92 - clocks: handles to fclk and pll clock
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| D | ti,dra7-dss.txt | 14 - clocks: handle to fclk
47 - clocks: handle to fclk
66 - clocks: handles to fclk and pll clock
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| /linux-6.14.4/drivers/media/dvb-frontends/ |
| D | s5h1420.c | 39 u32 fclk; member
368 tmp = state->fclk / tmp; in s5h1420_read_status()
475 do_div(val, (state->fclk / 1000)); in s5h1420_setsymbolrate()
501 * divide fclk by 1000000 to get the correct value. */ in s5h1420_setfreqoffset()
502 val = -(int) ((freqoffset * (1<<24)) / (state->fclk / 1000000)); in s5h1420_setfreqoffset()
529 * divide fclk by 1000000 to get the correct value. */ in s5h1420_getfreqoffset()
530 val = (((-val) * (state->fclk/1000000)) / (1<<24)); in s5h1420_getfreqoffset()
666 /* set s5h1420 fclk PLL according to desired symbol rate */ in s5h1420_set_frontend()
668 state->fclk = 80000000; in s5h1420_set_frontend()
670 state->fclk = 59000000; in s5h1420_set_frontend()
[all …]
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| D | cx24110.c | 50 {0x07,0x01}, /* @ Fclk, i.e. sampling clock, 60MHz */
231 u32 tmp, fclk, BDRI; in cx24110_set_symbolrate() local
245 and set the PLL accordingly (R07[1:0] Fclk, R06[7:4] PLLmult, in cx24110_set_symbolrate()
251 fclk=90999000UL/2; in cx24110_set_symbolrate()
255 fclk=60666000UL; in cx24110_set_symbolrate()
259 fclk=80888000UL; in cx24110_set_symbolrate()
263 fclk=90999000UL; in cx24110_set_symbolrate()
265 dprintk("cx24110 debug: fclk %d Hz\n",fclk); in cx24110_set_symbolrate()
275 BDRI=fclk>>2; in cx24110_set_symbolrate()
288 dprintk("fclk = %d\n", fclk); in cx24110_set_symbolrate()
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| D | mb86a20s.h | 16 * @fclk: Clock frequency. If zero, assumes the default
22 u32 fclk; member
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| /linux-6.14.4/drivers/clk/nuvoton/ |
| D | clk-ma35d1-pll.c | 146 unsigned long tmp, fout, fclk, diff; in ma35d1_pll_find_closest() local
153 fclk = div_u64(parent_rate * n, m); in ma35d1_pll_find_closest()
156 fclk = div_u64(fclk, 100); in ma35d1_pll_find_closest()
158 if (fclk < PLL_FCLK_MIN_FREQ || in ma35d1_pll_find_closest()
159 fclk > PLL_FCLK_MAX_FREQ) in ma35d1_pll_find_closest()
162 fout = div_u64(fclk, p); in ma35d1_pll_find_closest()
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| /linux-6.14.4/drivers/gpu/drm/hisilicon/hibmc/dp/ |
| D | dp_hw.c | 53 u32 fclk; /* flink_clock */ in hibmc_dp_set_sst() local
55 fclk = dp->link.cap.link_rate * HIBMC_DP_LINK_RATE_CAL; in hibmc_dp_set_sst()
61 htotal_size = htotal_int * fclk / (HIBMC_DP_SYMBOL_PER_FCLK * (mode->clock / 1000)); in hibmc_dp_set_sst()
64 hblank_size = hblank_int * fclk * 9947 / in hibmc_dp_set_sst()
69 drm_dbg_dp(dp->dev, "flink_clock %u pixel_clock %d", fclk, mode->clock / 1000); in hibmc_dp_set_sst()
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| /linux-6.14.4/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/ |
| D | dml2_dpmm_dcn4.c | 24 double *fclk, in get_minimum_clocks_for_latency() argument
35 *fclk = in_out->min_clk_table->dram_bw_table.entries[min_clock_index_for_latency].min_fclk_khz; in get_minimum_clocks_for_latency()
289 result = round_up_to_next_dpm(&display_cfg->min_clocks.dcn4x.active.fclk_khz, &state_table->fclk); in map_soc_min_clocks_to_dpm_fine_grained()
296 …t = round_up_to_next_dpm(&display_cfg->min_clocks.dcn4x.svp_prefetch.fclk_khz, &state_table->fclk); in map_soc_min_clocks_to_dpm_fine_grained()
303 result = round_up_to_next_dpm(&display_cfg->min_clocks.dcn4x.idle.fclk_khz, &state_table->fclk); in map_soc_min_clocks_to_dpm_fine_grained()
310 …o_next_dpm(&display_cfg->min_clocks.dcn4x.svp_prefetch_no_throttle.fclk_khz, &state_table->fclk) || in map_soc_min_clocks_to_dpm_fine_grained()
329 display_cfg->min_clocks.dcn4x.active.fclk_khz <= state_table->fclk.clk_values_khz[index] && in map_soc_min_clocks_to_dpm_coarse_grained()
332 display_cfg->min_clocks.dcn4x.active.fclk_khz = state_table->fclk.clk_values_khz[index]; in map_soc_min_clocks_to_dpm_coarse_grained()
343 display_cfg->min_clocks.dcn4x.idle.fclk_khz <= state_table->fclk.clk_values_khz[index] && in map_soc_min_clocks_to_dpm_coarse_grained()
346 display_cfg->min_clocks.dcn4x.idle.fclk_khz = state_table->fclk.clk_values_khz[index]; in map_soc_min_clocks_to_dpm_coarse_grained()
[all …]
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| /linux-6.14.4/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/ |
| D | smu_v13_0_1_ppsmc.h | 64 #define PPSMC_MSG_SetSoftMinFclk 0x14 ///< Set hard min for FCLK
68 #define PPSMC_MSG_GetFclkFrequency 0x18 ///< Get FCLK frequency
74 #define PPSMC_MSG_SetSoftMaxFclkByFreq 0x1E ///< Set soft max for FCLK
79 #define PPSMC_MSG_SetHardMinFclkByFreq 0x23 ///< Set hard min for FCLK
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| D | smu_v13_0_4_ppsmc.h | 73 #define PPSMC_MSG_SetSoftMinFclk 0x14 ///< Set hard min for FCLK
79 #define PPSMC_MSG_GetFclkFrequency 0x18 ///< Get FCLK frequency
86 #define PPSMC_MSG_SetSoftMaxFclkByFreq 0x1E ///< Set soft max for FCLK
92 #define PPSMC_MSG_SetHardMinFclkByFreq 0x23 ///< Set hard min for FCLK
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| D | smu_v14_0_0_ppsmc.h | 73 #define PPSMC_MSG_SetSoftMinFclk 0x14 ///< Set hard min for FCLK
77 #define PPSMC_MSG_spare_0x18 0x18 ///< Get FCLK frequency
83 #define PPSMC_MSG_SetSoftMaxFclkByFreq 0x1E ///< Set soft max for FCLK
88 #define PPSMC_MSG_SetHardMinFclkByFreq 0x23 ///< Set hard min for FCLK
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| /linux-6.14.4/drivers/iio/adc/ |
| D | ad7124.c | 274 unsigned int fclk, odr_sel_bits; in ad7124_set_channel_odr() local
276 fclk = clk_get_rate(st->mclk); in ad7124_set_channel_odr()
278 * FS[10:0] = fCLK / (fADC x 32) where: in ad7124_set_channel_odr()
280 * fCLK is the master clock frequency in ad7124_set_channel_odr()
284 odr_sel_bits = DIV_ROUND_CLOSEST(fclk, odr * 32); in ad7124_set_channel_odr()
293 /* fADC = fCLK / (FS[10:0] x 32) */ in ad7124_set_channel_odr()
294 st->channels[channel].cfg.odr = DIV_ROUND_CLOSEST(fclk, odr_sel_bits * 32); in ad7124_set_channel_odr()
1008 unsigned int fclk, power_mode; in ad7124_setup() local
1011 fclk = clk_get_rate(st->mclk); in ad7124_setup()
1012 if (!fclk) in ad7124_setup()
[all …]
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| /linux-6.14.4/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| D | vg_clk_mgr.c | 399 /* We will not select WM based on fclk, so leave it as unconstrained */ in vg_build_watermark_ranges()
570 "number of reported FCLK DPM levels exceeds maximum"); in vg_clk_mgr_helper_populate_bw_params()
572 /* Find lowest DPM, FCLK is filled in reverse order*/ in vg_clk_mgr_helper_populate_bw_params()
575 if (clock_table->DfPstateTable[i].fclk != 0) { in vg_clk_mgr_helper_populate_bw_params()
590 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].fclk; in vg_clk_mgr_helper_populate_bw_params()
595 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].fclk; in vg_clk_mgr_helper_populate_bw_params()
632 { .fclk = 400, .memclk = 400, .voltage = 2800 },
633 { .fclk = 400, .memclk = 400, .voltage = 2800 },
634 { .fclk = 400, .memclk = 400, .voltage = 2800 },
635 { .fclk = 400, .memclk = 400, .voltage = 2800 }
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| /linux-6.14.4/arch/sh/drivers/pci/ |
| D | pcie-sh7786.c | 26 struct clk *fclk, phy_clk; member
224 port->fclk = clk_get(NULL, fclk_name); in pcie_clk_init()
225 if (IS_ERR(port->fclk)) { in pcie_clk_init()
226 ret = PTR_ERR(port->fclk); in pcie_clk_init()
230 clk_enable(port->fclk); in pcie_clk_init()
250 clk_disable(port->fclk); in pcie_clk_init()
251 clk_put(port->fclk); in pcie_clk_init()
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| /linux-6.14.4/drivers/pwm/ |
| D | pwm-omap-dmtimer.c | 154 struct clk *fclk; in pwm_omap_dmtimer_config() local
163 fclk = omap->pdata->get_fclk(omap->dm_timer); in pwm_omap_dmtimer_config()
164 if (!fclk) { in pwm_omap_dmtimer_config()
165 dev_err(pwmchip_parent(chip), "invalid pmtimer fclk\n"); in pwm_omap_dmtimer_config()
169 clk_rate = clk_get_rate(fclk); in pwm_omap_dmtimer_config()
171 dev_err(pwmchip_parent(chip), "invalid pmtimer fclk rate\n"); in pwm_omap_dmtimer_config()
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| /linux-6.14.4/drivers/clocksource/ |
| D | timer-ti-dm.c | 122 struct clk *fclk; member
417 if (unlikely(!timer) || IS_ERR(timer->fclk)) in omap_dm_timer_set_source()
446 if (clk_hw_get_num_parents(__clk_get_hw(timer->fclk)) < 2) in omap_dm_timer_set_source()
456 ret = clk_set_parent(timer->fclk, parent); in omap_dm_timer_set_source()
728 if (timer && !IS_ERR(timer->fclk)) in omap_dm_timer_get_fclk()
729 return timer->fclk; in omap_dm_timer_get_fclk()
1139 timer->fclk = devm_clk_get(dev, "fck"); in omap_dm_timer_probe()
1140 if (IS_ERR(timer->fclk)) in omap_dm_timer_probe()
1141 return PTR_ERR(timer->fclk); in omap_dm_timer_probe()
1144 ret = devm_clk_notifier_register(dev, timer->fclk, in omap_dm_timer_probe()
[all …]
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| /linux-6.14.4/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| D | dcn314_clk_mgr.c | 499 /* We will not select WM based on fclk, so leave it as unconstrained */ in dcn314_build_watermark_ranges()
626 /* Find highest valid fclk pstate */ in dcn314_clk_mgr_helper_populate_bw_params()
628 if (is_valid_clock_value(clock_table->DfPstateTable[i].FClk) && in dcn314_clk_mgr_helper_populate_bw_params()
629 clock_table->DfPstateTable[i].FClk > max_fclk) { in dcn314_clk_mgr_helper_populate_bw_params()
630 max_fclk = clock_table->DfPstateTable[i].FClk; in dcn314_clk_mgr_helper_populate_bw_params()
635 /* We expect the table to contain at least one valid fclk entry. */ in dcn314_clk_mgr_helper_populate_bw_params()
650 uint32_t min_fclk = clock_table->DfPstateTable[0].FClk; in dcn314_clk_mgr_helper_populate_bw_params()
654 if (is_valid_clock_value(clock_table->DfPstateTable[j].FClk) && in dcn314_clk_mgr_helper_populate_bw_params()
655 clock_table->DfPstateTable[j].FClk < min_fclk && in dcn314_clk_mgr_helper_populate_bw_params()
657 min_fclk = clock_table->DfPstateTable[j].FClk; in dcn314_clk_mgr_helper_populate_bw_params()
[all …]
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| /linux-6.14.4/Documentation/devicetree/bindings/mmc/ |
| D | ti-omap-hsmmc.txt | 92 swakeup | | fclk
98 In suspend the fclk is off and the module is dysfunctional. Even register reads
99 will fail. A small logic in the host will request fclk restore, when an
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| /linux-6.14.4/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/ |
| D | dcn401_clk_mgr_smu_msg.c | 144 smu_print("FCLK P-state support value is : %d\n", support); in dcn401_smu_send_fclk_pstate_message()
270 /* 15:0 for uclk, 32:16 for fclk */ in dcn401_smu_set_idle_uclk_fclk_hardmin()
292 /* 15:0 for uclk, 32:16 for fclk */ in dcn401_smu_set_active_uclk_fclk_hardmin()
314 /* 15:0 for uclk, 32:16 for fclk */ in dcn401_smu_set_subvp_uclk_fclk_hardmin()
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| /linux-6.14.4/sound/soc/ti/ |
| D | omap-dmic.c | 36 struct clk *fclk; member
320 dev_err(dmic->dev, "fclk clk_id (%d) not supported\n", clk_id); in omap_dmic_select_fclk()
330 mux = clk_get_parent(dmic->fclk); in omap_dmic_select_fclk()
476 dmic->fclk = devm_clk_get(dmic->dev, "fck"); in asoc_dmic_probe()
477 if (IS_ERR(dmic->fclk)) { in asoc_dmic_probe()
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