Lines Matching full:fclk
274 unsigned int fclk, odr_sel_bits; in ad7124_set_channel_odr() local
276 fclk = clk_get_rate(st->mclk); in ad7124_set_channel_odr()
278 * FS[10:0] = fCLK / (fADC x 32) where: in ad7124_set_channel_odr()
280 * fCLK is the master clock frequency in ad7124_set_channel_odr()
284 odr_sel_bits = DIV_ROUND_CLOSEST(fclk, odr * 32); in ad7124_set_channel_odr()
293 /* fADC = fCLK / (FS[10:0] x 32) */ in ad7124_set_channel_odr()
294 st->channels[channel].cfg.odr = DIV_ROUND_CLOSEST(fclk, odr_sel_bits * 32); in ad7124_set_channel_odr()
1008 unsigned int fclk, power_mode; in ad7124_setup() local
1011 fclk = clk_get_rate(st->mclk); in ad7124_setup()
1012 if (!fclk) in ad7124_setup()
1018 fclk); in ad7124_setup()
1019 if (fclk != ad7124_master_clk_freq_hz[power_mode]) { in ad7124_setup()
1020 ret = clk_set_rate(st->mclk, fclk); in ad7124_setup()