| /linux-6.14.4/Documentation/gpu/ |
| D | drm-usage-stats.rst | 1 .. _drm-client-usage-stats:
8 `fops->show_fdinfo()` as part of the driver specific file operations registered
15 output is split between common and driver specific parts. Having said that,
22 - File shall contain one key value pair per one line of text.
23 - Colon character (`:`) must be used to delimit keys and values.
24 - All keys shall be prefixed with `drm-`.
25 - Whitespace between the delimiter and first non-whitespace character shall be
27 - Keys are not allowed to contain whitespace characters.
28 - Numerical key value pairs can end with optional unit string.
29 - Data type of the value is fixed as defined in the specification.
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| /linux-6.14.4/drivers/leds/ |
| D | leds-lp55xx-common.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
9 * Derived from leds-lp5521.c, leds-lp5523.c
15 #include <linux/led-class-multicolor.h>
53 static LP55XX_DEV_ATTR_RW(engine##nr##_mode, show_engine##nr##_mode, \
69 static LP55XX_DEV_ATTR_RW(engine##nr##_leds, show_engine##nr##_leds, \
79 static LP55XX_DEV_ATTR_WO(engine##nr##_load, store_engine##nr##_load)
116 * @reg_op_mode : Chip specific OP MODE reg addr
117 * @engine_busy : Chip specific engine busy
119 * @reset : Chip specific reset command
120 * @enable : Chip specific enable command
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| /linux-6.14.4/Documentation/leds/ |
| D | leds-lp55xx.rst | 8 -----------
14 Device attributes for user-space interface
47 To support device specific configurations, special structure
50 - Maximum number of channels
51 - Reset command, chip enable command
52 - Chip specific initialization
53 - Brightness control register access
54 - Setting LED output current
55 - Program memory address access for running patterns
56 - Additional device specific attributes
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| D | leds-lp5562.rst | 15 All four channels can be also controlled using the engine micro programs.
17 For the details, please refer to 'firmware' section in leds-lp55xx.txt
24 Therefore each channel should be mapped to the engine number.
29 Unlike the LP5521/LP5523/55231, LP5562 has unique feature for the engine mux,
35 Red ... Engine 1 (fixed)
36 Green ... Engine 2 (fixed)
37 Blue ... Engine 3 (fixed)
38 White ... Engine 1 or 2 or 3 (selective)
45 the engine selection and loading the firmware.
46 Engine mux has two different mode, RGB and W.
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| /linux-6.14.4/Documentation/driver-api/dmaengine/ |
| D | client.rst | 2 DMA Engine API Guide
7 .. note:: For DMA Engine usage in async_tx please see:
8 ``Documentation/crypto/async-tx-api.rst``
11 Below is a guide to device driver writers on how to use the Slave-DMA API of the
12 DMA Engine. This is applicable only for slave DMA usage only.
19 - Allocate a DMA slave channel
21 - Set slave and controller specific parameters
23 - Get a descriptor for transaction
25 - Submit the transaction
27 - Issue pending requests and wait for callback notification
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| /linux-6.14.4/Documentation/devicetree/bindings/mtd/ |
| D | nand-chip.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-chip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <[email protected]>
13 - $ref: mtd.yaml#
18 SPI-NAND devices are concerned by this description.
23 Contains the chip-select IDs.
25 nand-ecc-engine:
27 A phandle on the hardware ECC engine if any. There are
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| /linux-6.14.4/drivers/gpu/drm/sun4i/ |
| D | sunxi_engine.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
18 * struct sunxi_engine_ops - helper operations for sunXi engines
27 * This callback allows to prepare our engine for an atomic
34 void (*atomic_begin)(struct sunxi_engine *engine,
40 * This callback allows to validate plane-update related CRTC
41 * constraints specific to engines. This is mirroring the
51 int (*atomic_check)(struct sunxi_engine *engine,
63 void (*commit)(struct sunxi_engine *engine,
71 * the layers supported by that engine.
81 struct sunxi_engine *engine);
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| /linux-6.14.4/Documentation/devicetree/bindings/fsi/ |
| D | fsi.txt | 1 FSI bus & engine generic device tree bindings
4 The FSI bus is probe-able, so the OS is able to enumerate FSI slaves, and
6 nodes to probed engines. This allows for fsi engines to expose non-probeable
7 busses, which are then exposed by the device tree. For example, an FSI engine
8 that is an I2C master - the I2C bus can be described by the device tree under
9 the engine's device tree node.
13 the fsi-master-* binding specifications.
18 fsi-master {
19 /* top-level of FSI bus topology, bound to an FSI master driver and
22 fsi-slave@<link,id> {
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| /linux-6.14.4/Documentation/gpu/amdgpu/ |
| D | driver-core.rst | 17 the SoC itself rather than specific IPs. E.g., things like GPU resets
23 SMU, PSP, etc.). Specific components (CPU, GPU, etc.) usually have
32 This was a dedicated IP on older pre-vega chips, but has since
34 have dedicated memory hubs for specific IPs or groups of IPs. We
58 It is described in more details in :ref:`Display Core <amdgpu-display-core>`.
61 This is a multi-purpose DMA engine. The kernel driver uses it for
67 This is the graphics and compute engine, i.e., the block that
69 largest block on the GPU. The 3D pipeline has tons of sub-blocks. In
75 This is the multi-media engine. It handles video and image encode and
76 decode. It's exposed to userspace for user mode drivers (VA-API,
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| /linux-6.14.4/drivers/gpu/drm/i915/gt/ |
| D | intel_engine_pm.c | 1 // SPDX-License-Identifier: MIT
20 static void intel_gsc_idle_msg_enable(struct intel_engine_cs *engine) in intel_gsc_idle_msg_enable() argument
22 struct drm_i915_private *i915 = engine->i915; in intel_gsc_idle_msg_enable()
24 if (MEDIA_VER(i915) >= 13 && engine->id == GSC0) { in intel_gsc_idle_msg_enable()
25 intel_uncore_write(engine->gt->uncore, in intel_gsc_idle_msg_enable()
29 intel_uncore_write(engine->gt->uncore, in intel_gsc_idle_msg_enable()
40 if (ce->state) { in dbg_poison_ce()
41 struct drm_i915_gem_object *obj = ce->state->obj; in dbg_poison_ce()
42 int type = intel_gt_coherent_map_type(ce->engine->gt, obj, true); in dbg_poison_ce()
50 memset(map, CONTEXT_REDZONE, obj->base.size); in dbg_poison_ce()
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| D | intel_engine_heartbeat.c | 1 // SPDX-License-Identifier: MIT
17 * While the engine is active, we send a periodic pulse along the engine
18 * to check on its health and to flush any idle-barriers. If that request
19 * is stuck, and we fail to preempt it, we declare the engine hung and
20 * issue a reset -- in the hope that restores progress.
23 static bool next_heartbeat(struct intel_engine_cs *engine) in next_heartbeat() argument
28 delay = READ_ONCE(engine->props.heartbeat_interval_ms); in next_heartbeat()
30 rq = engine->heartbeat.systole; in next_heartbeat()
35 * selftests which override the value and expect specific behaviour. in next_heartbeat()
37 * heartbeat periods (or to override the pre-emption timeout as well, in next_heartbeat()
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| D | intel_workarounds.c | 1 // SPDX-License-Identifier: MIT
3 * Copyright © 2014-2018 Intel Corporation
30 * - Context workarounds: workarounds that touch registers that are
40 * - Engine workarounds: the list of these WAs is applied whenever the specific
41 * engine is reset. It's also possible that a set of engine classes share a
45 * driver is to tie those workarounds to the first compute/render engine that
46 * is registered. When executing with GuC submission, engine resets are
48 * written once, on engine initialization, and then passed to GuC, that
52 * Workarounds for registers specific to RCS and CCS should be implemented in
55 * xcs_engine_wa_init(). Workarounds for registers not belonging to a specific
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| D | intel_gt.h | 1 /* SPDX-License-Identifier: MIT */
23 ((gt)->type != GT_MEDIA && \
24 GRAPHICS_VER_FULL((gt)->i915) >= (from) && \
25 GRAPHICS_VER_FULL((gt)->i915) <= (until)))
37 ((gt) && (gt)->type == GT_MEDIA && \
38 MEDIA_VER_FULL((gt)->i915) >= (from) && \
39 MEDIA_VER_FULL((gt)->i915) <= (until)))
42 * Check that the GT is a graphics GT with a specific IP version and has
44 * inclusive, the upper bound is exclusive. The most common use-case of this
59 IS_GRAPHICS_STEP((gt)->i915, (from), (until))))
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| /linux-6.14.4/drivers/dma/amd/ptdma/ |
| D | ptdma.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * -- Based on the CCP driver
25 #include "../../virt-dma.h"
94 #define QUEUE_SIZE_VAL ((ffs(CMD_Q_LEN) - 2) & \
96 #define Q_PTR_MASK (2 << (QUEUE_SIZE_VAL + 5) - 1)
109 #define LSB_COUNT (LSB_END - LSB_START + 1)
124 * struct pt_passthru_engine - pass-through operation
133 * - bit_mod, byte_swap, src, dst, src_len
134 * - mask, mask_len if bit_mod is not PT_PASSTHRU_BITWISE_NOOP
145 * struct pt_cmd - PTDMA operation request
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| /linux-6.14.4/Documentation/arch/powerpc/ |
| D | vas-api.rst | 1 .. SPDX-License-Identifier: GPL-2.0
2 .. _VAS-API:
12 allows both userspace and kernel communicate to co-processor
14 unit comprises of one or more hardware engines or co-processor types
16 userspace applications will have access to only GZIP Compression engine
21 Requests to the GZIP engine must be formatted as a co-processor Request
24 the engine's request queue.
26 The GZIP engine provides two priority levels of requests: Normal and
37 Application access to the GZIP engine is provided through
38 /dev/crypto/nx-gzip device node implemented by the VAS/NX device driver.
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| /linux-6.14.4/drivers/gpu/drm/amd/display/ |
| D | Kconfig | 1 # SPDX-License-Identifier: MIT
2 # Copyright © 2019-2024 Advanced Micro Devices, Inc. All rights reserved.
4 menu "Display Engine Configuration"
8 bool "AMD DC - Enable new display engine"
17 Choose this option if you want to use the new display engine
26 https://github.com/llvm/llvm-project/issues/41896.
31 Floating point support, required for DCN-based SoCs
56 This option enables the calculation of crc of specific region via
57 debugfs. Cooperate with specific DMCU FW.
|
| /linux-6.14.4/drivers/crypto/marvell/cesa/ |
| D | cesa.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
8 #include <linux/dma-direction.h>
70 * in Errata 4.12. It looks like that it was part of an IRQ-controller in FPGA
124 * /-----------\ 0
126 * |-----------| 0x20
128 * |-----------| 0x40
130 * |-----------| 0x40 (inplace)
132 * |-----------| 0x80
133 * | DATA IN | 16 * x (max ->max_req_size)
134 * |-----------| 0x80 (inplace operation)
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| /linux-6.14.4/drivers/accel/habanalabs/gaudi2/ |
| D | gaudi2P.h | 1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright 2020-2022 HabanaLabs, Ltd.
19 #define GAUDI2_LINUX_FW_FILE "habanalabs/gaudi2/gaudi2-fit.itb"
20 #define GAUDI2_BOOT_FIT_FILE "habanalabs/gaudi2/gaudi2-boot-fit.itb"
44 (((mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8191 - \
48 (((mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2047 - \
56 #define NUM_OF_EXPOSED_SM_BLOCKS ((NUM_OF_DCORES - 1) * 2)
73 #define SM_OBJS_BLOCK_SIZE (mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_0 - \
105 (GAUDI2_DCORE1_ENGINE_ID_EDMA_0 - GAUDI2_DCORE0_ENGINE_ID_EDMA_0)
138 #define VA_HOST_SPACE_PAGE_SIZE (VA_HOST_SPACE_PAGE_END - VA_HOST_SPACE_PAGE_START)
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| /linux-6.14.4/Documentation/crypto/ |
| D | async-tx-api.rst | 1 .. SPDX-License-Identifier: GPL-2.0
32 bulk memory transfers/transforms with support for inter-transactional
34 the details of different hardware offload engine implementations. Code
43 xor-parity-calculations of the md-raid5 driver using the offload engines
51 operation will be offloaded when an engine is available and carried out
54 operations to be submitted, like xor->copy->xor in the raid5 case. The
64 -----------------------------
69 async_<operation>(<op specific parameters>, struct async_submit_ctl *submit)
72 ------------------------
92 -------------------------
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| /linux-6.14.4/drivers/net/ethernet/hisilicon/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
16 for your specific card in the following questions.
36 ports at 10/100 Mbps in full-duplex or half-duplex mode.
71 is needed by any driver which provides HNS acceleration engine or make
72 use of the engine
80 acceleration engine support. The engine is used in Hisilicon hip05,
98 This layer facilitates clients like ENET, RoCE and user-space ethernet
105 tristate "Hisilicon HNS3 HCLGE Acceleration Engine & Compatibility Layer Support"
110 This selects the HNS3_HCLGE network acceleration engine & its hardware
111 compatibility layer. The engine would be used in Hisilicon hip08 family of
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| /linux-6.14.4/drivers/crypto/marvell/octeontx2/ |
| D | otx2_cptpf_ucode.h | 1 /* SPDX-License-Identifier: GPL-2.0-only
16 * IE and SE engines can be attached to the same engine group.
35 OTX2_CPT_AE_UC_TYPE = 1, /* AE-MAIN */
36 OTX2_CPT_SE_UC_TYPE1 = 20,/* SE-MAIN - combination of 21 and 22 */
42 OTX2_CPT_IE_UC_TYPE1 = 30, /* IE-MAIN - combination of 31 and 32 */
94 /* Maximum and current number of engines available for all engine groups */
104 /* Engines reserved to an engine group */
106 int type; /* engine type */
108 int offset; /* constant offset of engine type in the bitmap */
115 * is mirroring enabled, it is set only for engine
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| /linux-6.14.4/drivers/crypto/hisilicon/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
12 Support for Hisilicon SEC Engine in Hip06 and Hip07
35 Support for HiSilicon SEC Engine of version 2 in crypto subsystem.
50 interface. Specific engine driver may use this module.
75 Support for HiSilicon HPRE(High Performance RSA Engine)
|
| /linux-6.14.4/include/linux/mtd/ |
| D | nand.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright 2017 - Free Electrons
6 * Boris Brezillon <boris.brezillon@free-electrons.com>
18 * struct nand_memory_organization - Memory organization structure
55 * struct nand_row_converter - Information needed to convert an absolute offset
67 * struct nand_pos - NAND position object
74 * These information are usually used by specific sub-layers to select the
86 * enum nand_page_io_req_type - Direction of an I/O request
96 * struct nand_page_io_req - NAND I/O request object
109 * This object is used to pass per-page I/O requests to NAND sub-layers. This
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| /linux-6.14.4/drivers/gpu/drm/amd/include/ |
| D | amd_shared.h | 73 * enum amd_ip_block_type - Used to classify IP blocks by functionality.
80 * @AMD_IP_BLOCK_TYPE_DCE: Display and Compositing Engine
81 * @AMD_IP_BLOCK_TYPE_GFX: Graphics and Compute Engine
82 * @AMD_IP_BLOCK_TYPE_SDMA: System DMA Engine
84 * @AMD_IP_BLOCK_TYPE_VCE: Video Compression Engine
85 * @AMD_IP_BLOCK_TYPE_ACP: Audio Co-Processor
87 * @AMD_IP_BLOCK_TYPE_MES: Micro-Engine Scheduler
88 * @AMD_IP_BLOCK_TYPE_JPEG: JPEG Engine
89 * @AMD_IP_BLOCK_TYPE_VPE: Video Processing Engine
185 * enum PP_FEATURE_MASK - Used to mask power play features.
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| /linux-6.14.4/drivers/gpu/drm/xe/ |
| D | xe_exec_queue_types.h | 1 /* SPDX-License-Identifier: MIT */
25 XE_EXEC_QUEUE_PRIORITY_UNSET = -2, /* For execlist usage only */
35 * struct xe_exec_queue - Execution queue
47 * @hwe: A hardware of the same class. May (physical engine) or may not
48 * (virtual engine) be where jobs actual engine up running. Should never
66 /** @msix_vec: MSI-X vector (for platforms that support it) */
72 * @last_fence: last fence on exec queue, protected by vm->lock in write
73 * mode if bind exec queue, protected by dma resv lock if non-bind exec
80 /* kernel engine only destroyed at driver unload */
84 /* child of VM queue for multi-tile VM jobs */
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