Lines Matching +full:engine +full:- +full:specific
1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright 2020-2022 HabanaLabs, Ltd.
19 #define GAUDI2_LINUX_FW_FILE "habanalabs/gaudi2/gaudi2-fit.itb"
20 #define GAUDI2_BOOT_FIT_FILE "habanalabs/gaudi2/gaudi2-boot-fit.itb"
44 (((mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8191 - \
48 (((mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2047 - \
56 #define NUM_OF_EXPOSED_SM_BLOCKS ((NUM_OF_DCORES - 1) * 2)
73 #define SM_OBJS_BLOCK_SIZE (mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_0 - \
105 (GAUDI2_DCORE1_ENGINE_ID_EDMA_0 - GAUDI2_DCORE0_ENGINE_ID_EDMA_0)
138 #define VA_HOST_SPACE_PAGE_SIZE (VA_HOST_SPACE_PAGE_END - VA_HOST_SPACE_PAGE_START)
141 #define VA_HOST_SPACE_HPAGE_SIZE (VA_HOST_SPACE_HPAGE_END - VA_HOST_SPACE_HPAGE_START)
153 * address space which is determined at run-time.
213 /* RAZWI initiator coordinates- X- 5 bits, Y- 4 bits */
233 #define HW_CAP_NIC_MASK GENMASK_ULL(NIC_NUMBER_OF_ENGINES - 1, 0)
240 #define GAUDI2_NUM_TESTED_QS (GAUDI2_QUEUE_ID_CPU_PQ - GAUDI2_QUEUE_ID_PDMA_0_0)
246 GAUDI2_RESERVED_SOB_CS_COMPLETION_FIRST + GAUDI2_MAX_PENDING_CS - 1,
250 GAUDI2_RESERVED_SOB_DEC_NRM_FIRST + NUMBER_OF_DEC - 1,
253 GAUDI2_RESERVED_SOB_DEC_ABNRM_FIRST + NUMBER_OF_DEC - 1,
260 GAUDI2_RESERVED_MON_CS_COMPLETION_FIRST + GAUDI2_MAX_PENDING_CS - 1,
264 GAUDI2_RESERVED_MON_DEC_NRM_FIRST + 3 * NUMBER_OF_DEC - 1,
267 GAUDI2_RESERVED_MON_DEC_ABNRM_FIRST + 3 * NUMBER_OF_DEC - 1,
279 * At most- two faulty TPCs are allowed
280 * First replacement to a faulty TPC will be TPC24, second- TPC23
371 /* specific EDMA enumeration */
416 GAUDI2_IRQ_NUM_NIC_PORT_LAST = (GAUDI2_IRQ_NUM_NIC_PORT_FIRST + NIC_NUMBER_OF_PORTS - 1),
420 GAUDI2_IRQ_NUM_USER_LAST = (GAUDI2_IRQ_NUM_USER_FIRST + GAUDI2_NUM_USER_INTERRUPTS - 1),
422 GAUDI2_IRQ_NUM_RESERVED_LAST = (GAUDI2_MSIX_ENTRIES - GAUDI2_NUM_RESERVED_INTERRUPTS - 1),
424 GAUDI2_IRQ_NUM_LAST = (GAUDI2_MSIX_ENTRIES - 1)
430 * struct dup_block_ctx - context to initialize unit instances across multiple
434 * @instance_cfg_fn: instance specific configuration function.
439 * @enabled_mask: mask of enabled instances (1- enabled, 0- disabled).
455 * struct gaudi2_queues_test_info - Holds the address of a the messages used for testing the
466 * struct gaudi2_device - ASIC specific manage structure.
467 * @cpucp_info_get: get information on device from CPU-CP
473 * this memory region should be write-only.
477 * @virt_msix_db_cpu_addr: host memory page for the virtual MSI-X doorbell.
478 * @virt_msix_db_dma_addr: bus address of the page for the virtual MSI-X doorbell.
480 * @hw_cap_initialized: This field contains a bit per H/W engine. When that
481 * engine is initialized, that bit is set by the driver to
482 * signal we can use this engine in later code paths.
484 * engine.
485 * @active_hw_arc: This field contains a bit per ARC of an H/W engine with
486 * exception of TPC and NIC engines. Once an engine arc is
490 * of its corresponding ARC of the H/W engine.
491 * @dec_hw_cap_initialized: This field contains a bit per decoder H/W engine.
492 * When that engine is initialized, that bit is set by
493 * the driver to signal we can use this engine in later
496 * engine.
497 * @tpc_hw_cap_initialized: This field contains a bit per TPC H/W engine.
498 * When that engine is initialized, that bit is set by
499 * the driver to signal we can use this engine in later
502 * engine.
504 * Once an engine arc is initialized, its respective bit is
506 * corresponding ARC of the TPC engine.
507 * @nic_hw_cap_initialized: This field contains a bit per nic H/W engine.
509 * Once an engine arc is initialized, its respective bit is
511 * corresponding ARC of the NIC engine.
519 * @aux_ops: functions for core <-> aux drivers communication.