| /linux-6.14.4/drivers/net/ethernet/stmicro/stmmac/ |
| D | dwmac-sti.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dwmac-sti.c - STMicroelectronics DWMAC Specific Glue layer
5 * Copyright (C) 2003-2014 STMicroelectronics (R&D) Limited
40 * ------------------------------------------------
43 * ------------------------------------------------
45 *| | clk-125/txclk | txclk |
46 * ------------------------------------------------
48 *| | clk-125/txclk | clkgen |
50 * ------------------------------------------------
52 *| | |clkgen/phyclk-in |
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| D | dwmac-meson8b.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Amlogic Meson8b, Meson8m2 and GXBB DWMAC glue layer
10 #include <linux/clk-provider.h>
39 #define PRG_ETH0_TXDLY_MASK GENMASK(6, 5)
60 /* An internal counter based on the "timing-adjustment" clock. The counter is
84 int (*set_phy_mode)(struct meson8b_dwmac *dwmac);
107 static void meson8b_dwmac_mask_bits(struct meson8b_dwmac *dwmac, u32 reg, in meson8b_dwmac_mask_bits() argument
112 data = readl(dwmac->regs + reg); in meson8b_dwmac_mask_bits()
116 writel(data, dwmac->regs + reg); in meson8b_dwmac_mask_bits()
119 static struct clk *meson8b_dwmac_register_clk(struct meson8b_dwmac *dwmac, in meson8b_dwmac_register_clk() argument
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| D | dwmac-thead.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * T-HEAD DWMAC platform driver
24 #define GMAC_RX_CLK_N_EN BIT(5)
59 struct thead_dwmac *dwmac = plat->bsp_priv; in thead_dwmac_set_phy_if() local
62 switch (plat->mac_interface) { in thead_dwmac_set_phy_if()
73 dev_err(dwmac->dev, "unsupported phy interface %d\n", in thead_dwmac_set_phy_if()
74 plat->mac_interface); in thead_dwmac_set_phy_if()
75 return -EINVAL; in thead_dwmac_set_phy_if()
78 writel(phyif, dwmac->apb_base + GMAC_INTF_CTRL); in thead_dwmac_set_phy_if()
84 struct thead_dwmac *dwmac = plat->bsp_priv; in thead_dwmac_set_txclk_dir() local
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| D | dwmac-sun8i.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dwmac-sun8i.c - Allwinner sun8i DWMAC specific glue layer
11 #include <linux/mdio-mux.h>
28 /* General notes on dwmac-sun8i:
33 /* struct emac_variant - Describe dwmac-sun8i hardware variant
61 /* struct sunxi_priv_data - hold all sunxi private data
69 * @mux_handle: Internal pointer used by mdio-mux lib
147 * co-packaged AC200 chip instead.
197 #define EMAC_RX_TH_MASK GENMASK(5, 4)
233 #define EMAC_TX_EARLY_INT BIT(5)
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| D | dwmac-mediatek.c | 1 // SPDX-License-Identifier: GPL-2.0
24 #define RMII_CLK_SRC_INTERNAL BIT(5)
28 #define ETH_DLY_GTXC_ENABLE BIT(5)
50 #define MT8195_DLY_GTXC_ENABLE BIT(5)
58 #define MT8195_DLY_TXC_ENABLE BIT(5)
66 #define MT8195_DLY_RMII_TXC_ENABLE BIT(5)
114 int rmii_clk_from_mac = plat->rmii_clk_from_mac ? RMII_CLK_SRC_INTERNAL : 0; in mt2712_set_interface()
115 int rmii_rxc = plat->rmii_rxc ? RMII_CLK_SRC_RXC : 0; in mt2712_set_interface()
119 switch (plat->phy_mode) { in mt2712_set_interface()
133 dev_err(plat->dev, "phy interface not supported\n"); in mt2712_set_interface()
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| /linux-6.14.4/Documentation/devicetree/bindings/net/ |
| D | nxp,s32-dwmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright 2021-2024 NXP
4 ---
5 $id: http://devicetree.org/schemas/net/nxp,s32-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Jan Petrous (OSS) <[email protected]>
15 The SoC series S32G2xx and S32G3xx feature one DWMAC instance,
23 - const: nxp,s32g2-dwmac
24 - items:
25 - enum:
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| D | nxp,dwmac-imx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/nxp,dwmac-imx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8/9 DWMAC glue layer
10 - Clark Wang <[email protected]>
11 - Shawn Guo <[email protected]>
12 - NXP Linux Team <linux-[email protected]>
14 # We need a select here so we don't match all nodes with 'snps,dwmac'
20 - nxp,imx8mp-dwmac-eqos
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| D | starfive,jh7110-dwmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/starfive,jh7110-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: StarFive JH7110 DWMAC glue layer
11 - Emil Renner Berthing <[email protected]>
12 - Samin Guo <[email protected]>
19 - starfive,jh7100-dwmac
20 - starfive,jh7110-dwmac
22 - compatible
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| D | nxp,lpc1850-dwmac.txt | 7 - compatible: Should contain "nxp,lpc1850-dwmac"
12 compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac";
14 interrupts = <5>;
15 interrupt-names = "macirq";
17 clock-names = "stmmaceth";
19 reset-names = "stmmaceth";
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| D | mediatek-dwmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/mediatek-dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek DWMAC glue layer controller
10 - Biao Huang <[email protected]>
15 # We need a select here so we don't match all nodes with 'snps,dwmac'
21 - mediatek,mt2712-gmac
22 - mediatek,mt8188-gmac
23 - mediatek,mt8195-gmac
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| D | rockchip-dwmac.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/rockchip-dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David Wu <david.wu@rock-chips.com>
12 # We need a select here so we don't match all nodes with 'snps,dwmac'
18 - rockchip,px30-gmac
19 - rockchip,rk3128-gmac
20 - rockchip,rk3228-gmac
21 - rockchip,rk3288-gmac
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| /linux-6.14.4/Documentation/devicetree/bindings/reset/ |
| D | nxp,lpc1850-rgu.txt | 8 - compatible: Should be "nxp,lpc1850-rgu"
9 - reg: register base and length
10 - clocks: phandle and clock specifier to RGU clocks
11 - clock-names: should contain "delay" and "reg"
12 - #reset-cells: should be 1
20 12 ARM Cortex-M0 subsystem core (LPC43xx only)
56 56 ARM Cortex-M0 application core (LPC4370 only)
59 60 ADCHS (12-bit ADC) (LPC4370 only)
65 rgu: reset-controller@40053000 {
66 compatible = "nxp,lpc1850-rgu";
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| /linux-6.14.4/arch/arm64/boot/dts/freescale/ |
| D | imx8dxl-ss-conn.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+
6 /delete-node/ &enet1_lpcg;
7 /delete-node/ &fec2;
10 conn_enet0_root_clk: clock-conn-enet0-root {
11 compatible = "fixed-clock";
12 #clock-cells = <0>;
13 clock-frequency = <250000000>;
14 clock-output-names = "conn_enet0_root_clk";
17 clk_dummy: clock-dummy {
18 compatible = "fixed-clock";
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| /linux-6.14.4/arch/arm64/boot/dts/intel/ |
| D | socfpga_agilex.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/agilex-clock.h>
13 compatible = "intel,socfpga-agilex";
14 #address-cells = <2>;
15 #size-cells = <2>;
17 reserved-memory {
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| /linux-6.14.4/arch/arm64/boot/dts/altera/ |
| D | socfpga_stratix10.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
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| /linux-6.14.4/arch/arm/boot/dts/nxp/lpc/ |
| D | lpc18xx.dtsi | 9 * Released under the terms of 3-clause BSD License
14 #include "../../armv7-m.dtsi"
16 #include "dt-bindings/clock/lpc18xx-cgu.h"
17 #include "dt-bindings/clock/lpc18xx-ccu.h"
23 #address-cells = <1>;
24 #size-cells = <1>;
27 #address-cells = <1>;
28 #size-cells = <0>;
31 compatible = "arm,cortex-m3";
40 compatible = "fixed-clock";
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| /linux-6.14.4/arch/arm64/boot/dts/amlogic/ |
| D | meson-s4.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/meson-s4-gpio.h>
10 #include <dt-bindings/clock/amlogic,s4-pll-clkc.h>
11 #include <dt-bindings/clock/amlogic,s4-peripherals-clkc.h>
12 #include <dt-bindings/power/meson-s4-power.h>
13 #include <dt-bindings/reset/amlogic,meson-s4-reset.h>
17 #address-cells = <2>;
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| D | amlogic-c3.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/reset/amlogic,c3-reset.h>
10 #include <dt-bindings/clock/amlogic,c3-pll-clkc.h>
11 #include <dt-bindings/clock/amlogic,c3-scmi-clkc.h>
12 #include <dt-bindings/clock/amlogic,c3-peripherals-clkc.h>
13 #include <dt-bindings/power/amlogic,c3-pwrc.h>
14 #include <dt-bindings/gpio/amlogic-c3-gpio.h>
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| /linux-6.14.4/arch/arm/boot/dts/intel/socfpga/ |
| D | socfpga_arria10.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 enable-method = "altr,socfpga-a10-smp";
19 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
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| /linux-6.14.4/arch/arm/boot/dts/st/ |
| D | stih418-b2199.dts | 1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
11 compatible = "st,stih418-b2199", "st,stih418";
14 stdout-path = &sbc_serial0;
28 compatible = "gpio-leds";
29 led-red {
32 linux,default-trigger = "heartbeat";
34 led-green {
36 default-state = "off";
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| D | stm32mp135f-dhcor-dhsbc.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 * DHCR-STM32MP135F-C100-R051-EE-F0409-SPI4-RTC-WBT-I-01LG
7 * DHCOR PCB number: 718-100 or newer
8 * DHSBC PCB number: 719-100 or newer
11 /dts-v1/;
13 #include <dt-bindings/regulator/st,stm32mp13-regulator.h>
16 #include "stm32mp13xx-dhcor-som.dtsi"
20 compatible = "dh,stm32mp135f-dhcor-dhsbc",
21 "dh,stm32mp135f-dhcor-som",
32 stdout-path = "serial0:115200n8";
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| /linux-6.14.4/arch/arc/boot/dts/ |
| D | abilis_tb10x.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
12 compatible = "abilis,arc-tb10x";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 #address-cells = <1>;
18 #size-cells = <0>;
28 compatible = "snps,arc-timer";
30 interrupt-parent = <&intc>;
36 compatible = "snps,arc-timer";
41 #address-cells = <1>;
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| D | hsdk.dts | 1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/reset/snps,hsdk-reset.h>
18 #address-cells = <2>;
19 #size-cells = <2>;
22 … "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
30 #address-cells = <1>;
31 #size-cells = <0>;
62 input_clk: input-clk {
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| /linux-6.14.4/arch/mips/boot/dts/loongson/ |
| D | loongson64-2k1000.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include <dt-bindings/interrupt-controller/irq.h>
10 #address-cells = <2>;
11 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
21 #clock-cells = <1>;
27 #clock-cells = <0>;
28 compatible = "fixed-clock";
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| /linux-6.14.4/arch/mips/boot/dts/ni/ |
| D | 169445.dts | 1 /dts-v1/;
4 #address-cells = <1>;
5 #size-cells = <1>;
9 #address-cells = <1>;
10 #size-cells = <0>;
25 compatible = "fixed-clock";
26 #clock-cells = <0>;
27 clock-frequency = <50000000>;
30 cpu_intc: interrupt-controller {
31 #address-cells = <0>;
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