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/linux-6.14.4/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-meson8b.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Amlogic Meson8b, Meson8m2 and GXBB DWMAC glue layer
10 #include <linux/clk-provider.h>
30 #define PRG_ETH0_EXT_RMII_MODE 4
33 #define PRG_ETH0_CLK_M250_SEL_MASK GENMASK(4, 4)
35 /* TX clock delay in ns = "8ns / 4 * tx_dly_val" (where 8ns are exactly one
37 * 0ns = 0x0, 2ns = 0x1, 4ns = 0x2, 6ns = 0x3
60 /* An internal counter based on the "timing-adjustment" clock. The counter is
84 int (*set_phy_mode)(struct meson8b_dwmac *dwmac);
107 static void meson8b_dwmac_mask_bits(struct meson8b_dwmac *dwmac, u32 reg, in meson8b_dwmac_mask_bits() argument
[all …]
Ddwmac-thead.c1 // SPDX-License-Identifier: GPL-2.0
3 * T-HEAD DWMAC platform driver
23 #define GMAC_RX_CLK_EN BIT(4)
29 #define GMAC_RXCLK_DELAY GENMASK(4, 0)
33 #define GMAC_TXCLK_DELAY GENMASK(4, 0)
59 struct thead_dwmac *dwmac = plat->bsp_priv; in thead_dwmac_set_phy_if() local
62 switch (plat->mac_interface) { in thead_dwmac_set_phy_if()
73 dev_err(dwmac->dev, "unsupported phy interface %d\n", in thead_dwmac_set_phy_if()
74 plat->mac_interface); in thead_dwmac_set_phy_if()
75 return -EINVAL; in thead_dwmac_set_phy_if()
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Ddwmac-sti.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dwmac-sti.c - STMicroelectronics DWMAC Specific Glue layer
5 * Copyright (C) 2003-2014 STMicroelectronics (R&D) Limited
40 * ------------------------------------------------
43 * ------------------------------------------------
45 *| | clk-125/txclk | txclk |
46 * ------------------------------------------------
48 *| | clk-125/txclk | clkgen |
50 * ------------------------------------------------
52 *| | |clkgen/phyclk-in |
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Ddwmac-loongson1.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Loongson-1 DWMAC glue layer
5 * Copyright (C) 2011-2023 Keguang Zhang <[email protected]>
21 /* Loongson-1 SYSCON Registers */
25 /* Loongson-1B SYSCON Register Bits */
26 #define GMAC1_USE_UART1 BIT(4)
37 /* Loongson-1C SYSCON Register Bits */
42 #define PHY_INTF_RMII FIELD_PREP(PHY_INTF_SELI, 4)
51 struct ls1x_dwmac *dwmac = priv; in ls1b_dwmac_syscon_init() local
52 struct plat_stmmacenet_data *plat = dwmac->plat_dat; in ls1b_dwmac_syscon_init()
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Ddwmac-visconti.c1 // SPDX-License-Identifier: GPL-2.0
25 #define ETHER_CLK_SEL_DIV_SEL_2 BIT(4)
59 struct visconti_eth *dwmac = priv; in visconti_eth_fix_mac_speed() local
60 struct net_device *netdev = dev_get_drvdata(dwmac->dev); in visconti_eth_fix_mac_speed()
64 spin_lock_irqsave(&dwmac->lock, flags); in visconti_eth_fix_mac_speed()
67 val = readl(dwmac->reg + MAC_CTRL_REG); in visconti_eth_fix_mac_speed()
72 if (dwmac->phy_intf_sel == ETHER_CONFIG_INTF_RGMII) in visconti_eth_fix_mac_speed()
76 if (dwmac->phy_intf_sel == ETHER_CONFIG_INTF_RGMII) in visconti_eth_fix_mac_speed()
78 if (dwmac->phy_intf_sel == ETHER_CONFIG_INTF_RMII) in visconti_eth_fix_mac_speed()
83 if (dwmac->phy_intf_sel == ETHER_CONFIG_INTF_RGMII) in visconti_eth_fix_mac_speed()
[all …]
Ddwmac-starfive.c1 // SPDX-License-Identifier: GPL-2.0+
3 * StarFive DWMAC platform driver
36 struct starfive_dwmac *dwmac = priv; in starfive_dwmac_fix_mac_speed() local
42 dev_err(dwmac->dev, "invalid speed %u\n", speed); in starfive_dwmac_fix_mac_speed()
46 err = clk_set_rate(dwmac->clk_tx, rate); in starfive_dwmac_fix_mac_speed()
48 dev_err(dwmac->dev, "failed to set tx rate %lu\n", rate); in starfive_dwmac_fix_mac_speed()
53 struct starfive_dwmac *dwmac = plat_dat->bsp_priv; in starfive_dwmac_set_mode() local
59 switch (plat_dat->mac_interface) { in starfive_dwmac_set_mode()
72 dev_err(dwmac->dev, "unsupported interface %d\n", in starfive_dwmac_set_mode()
73 plat_dat->mac_interface); in starfive_dwmac_set_mode()
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Ddwmac-imx.c1 // SPDX-License-Identifier: GPL-2.0
3 * dwmac-imx.c - DWMAC Specific Glue layer for NXP imx8
40 #define MX93_GPR_CLK_SEL_OFFSET (4)
72 struct imx_priv_data *dwmac = plat_dat->bsp_priv; in imx8mp_set_intf_mode() local
75 switch (plat_dat->mac_interface) { in imx8mp_set_intf_mode()
81 val |= (dwmac->rmii_refclk_ext ? 0 : GPR_ENET_QOS_CLK_TX_CLK_SEL); in imx8mp_set_intf_mode()
91 pr_debug("imx dwmac doesn't support %d interface\n", in imx8mp_set_intf_mode()
92 plat_dat->mac_interface); in imx8mp_set_intf_mode()
93 return -EINVAL; in imx8mp_set_intf_mode()
97 return regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off, in imx8mp_set_intf_mode()
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Ddwmac-stm32.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * dwmac-stm32.c - DWMAC Specific Glue layer for STM32 MCU
37 *------------------------------------------
39 *------------------------------------------
41 *------------------------------------------
43 *------------------------------------------
45 *------------------------------------------
47 *------------------------------------------
64 #define SYSCFG_ETHCR_ETH_SEL_RGMII BIT(4)
74 * ---------------------------------------------------------------------------
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Ddwmac-anarion.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Adaptrum Anarion DWMAC glue layer
18 #define GMAC_SW_CONFIG_REG 4
29 return readl(gmac->ctl_block + reg); in gmac_read_reg()
34 writel(val, gmac->ctl_block + reg); in gmac_write_reg()
47 sw_config |= (gmac->phy_intf_sel & GMAC_CONFIG_INTF_SEL_MASK); in anarion_gmac_init()
72 dev_err(&pdev->dev, "Cannot get reset region (%d)!\n", err); in anarion_config_dt()
76 gmac = devm_kzalloc(&pdev->dev, sizeof(*gmac), GFP_KERNEL); in anarion_config_dt()
78 return ERR_PTR(-ENOMEM); in anarion_config_dt()
80 gmac->ctl_block = ctl_block; in anarion_config_dt()
[all …]
Ddwmac-intel.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * DWMAC Intel header file
20 #define SERDES_PWR_ST_MASK GENMASK(6, 4) /* Serdes Power state*/
25 #define SERDES_PWR_ST_SHIFT 4
40 /* Cross-timestamping defines */
Ddwmac-sun8i.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dwmac-sun8i.c - Allwinner sun8i DWMAC specific glue layer
11 #include <linux/mdio-mux.h>
28 /* General notes on dwmac-sun8i:
33 /* struct emac_variant - Describe dwmac-sun8i hardware variant
61 /* struct sunxi_priv_data - hold all sunxi private data
69 * @mux_handle: Internal pointer used by mdio-mux lib
147 * co-packaged AC200 chip instead.
197 #define EMAC_RX_TH_MASK GENMASK(5, 4)
199 #define EMAC_RX_TH_64 (0x1 << 4)
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/linux-6.14.4/Documentation/devicetree/bindings/net/
Dstarfive,jh7110-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/starfive,jh7110-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: StarFive JH7110 DWMAC glue layer
11 - Emil Renner Berthing <[email protected]>
12 - Samin Guo <[email protected]>
19 - starfive,jh7100-dwmac
20 - starfive,jh7110-dwmac
22 - compatible
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Dtoshiba,visconti-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/toshiba,visconti-dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Toshiba Visconti DWMAC Ethernet controller
10 - Nobuhiro Iwamatsu <[email protected]>
17 - toshiba,visconti-dwmac
19 - compatible
22 - $ref: snps,dwmac.yaml#
27 - items:
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Damlogic,meson-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/amlogic,meson-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Amlogic Meson DWMAC Ethernet controller
11 - Neil Armstrong <[email protected]>
12 - Martin Blumenstingl <[email protected]>
14 # We need a select here so we don't match all nodes with 'snps,dwmac'
20 - amlogic,meson6-dwmac
21 - amlogic,meson8b-dwmac
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Dsnps,dwmac.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/snps,dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Torgue <[email protected]>
11 - Giuseppe Cavallaro <[email protected]>
12 - Jose Abreu <[email protected]>
23 - snps,dwmac
24 - snps,dwmac-3.40a
25 - snps,dwmac-3.50a
[all …]
Dintel,dwmac-plat.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/intel,dwmac-plat.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel DWMAC glue layer
10 - Vineetha G. Jaya Kumaran <[email protected]>
17 - intel,keembay-dwmac
19 - compatible
22 - $ref: snps,dwmac.yaml#
27 - items:
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Dsocfpga-dwmac.txt1 Altera SOCFPGA SoC DWMAC controller
3 This is a variant of the dwmac/stmmac driver an inherits all descriptions
9 - compatible : For Cyclone5/Arria5 SoCs it should contain
10 "altr,socfpga-stmmac". For Arria10/Agilex/Stratix10 SoCs
11 "altr,socfpga-stmmac-a10-s10".
12 Along with "snps,dwmac" and any applicable more detailed
14 - altr,sysmgr-syscon : Should be the phandle to the system manager node that
20 - altr,f2h_ptp_ref_clk use f2h_ptp_ref_clk instead of default eosc1 clock
24 altr,emac-splitter: Should be the phandle to the emac splitter soft IP node if
25 DWMAC controller is connected emac splitter.
[all …]
Dqcom,ethqos.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <[email protected]>
11 - Konrad Dybcio <[email protected]>
18 - $ref: snps,dwmac.yaml#
23 - items:
24 - enum:
25 - qcom,qcs615-ethqos
26 - const: qcom,qcs404-ethqos
[all …]
/linux-6.14.4/arch/arm64/boot/dts/altera/
Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
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/linux-6.14.4/arch/arm64/boot/dts/st/
Dstm32mp253.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
11 compatible = "arm,cortex-a35";
14 enable-method = "psci";
15 power-domains = <&CPU_PD1>;
16 power-domain-names = "psci";
20 arm-pmu {
23 interrupt-affinity = <&cpu0>, <&cpu1>;
27 CPU_PD1: power-domain-cpu1 {
28 #power-domain-cells = <0>;
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/linux-6.14.4/arch/arm64/boot/dts/intel/
Dsocfpga_agilex.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/agilex-clock.h>
13 compatible = "intel,socfpga-agilex";
14 #address-cells = <2>;
15 #size-cells = <2>;
17 reserved-memory {
[all …]
/linux-6.14.4/arch/arm/boot/dts/st/
Dstm32mp133.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
14 reg-names = "m_can", "message_ram";
17 interrupt-names = "int0", "int1";
19 clock-names = "hclk", "cclk";
20 bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
27 reg-names = "m_can", "message_ram";
30 interrupt-names = "int0", "int1";
32 clock-names = "hclk", "cclk";
33 bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
[all …]
/linux-6.14.4/arch/riscv/boot/dts/thead/
Dth1520.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/clock/thead,th1520-clk-ap.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
18 timebase-frequency = <3000000>;
24 riscv,isa-base = "rv64i";
25 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
[all …]
/linux-6.14.4/arch/arm/boot/dts/intel/socfpga/
Dsocfpga_arria10.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 enable-method = "altr,socfpga-a10-smp";
19 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
[all …]
/linux-6.14.4/arch/arc/boot/dts/
Dabilis_tb10x.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
12 compatible = "abilis,arc-tb10x";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 #address-cells = <1>;
18 #size-cells = <0>;
28 compatible = "snps,arc-timer";
30 interrupt-parent = <&intc>;
36 compatible = "snps,arc-timer";
41 #address-cells = <1>;
[all …]

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