| /linux-6.14.4/Documentation/devicetree/bindings/usb/ |
| D | qcom,dwc3.yaml | 4 $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml#
7 title: Qualcomm SuperSpeed DWC3 USB SoC controller
16 - qcom,ipq4019-dwc3
17 - qcom,ipq5018-dwc3
18 - qcom,ipq5332-dwc3
19 - qcom,ipq5424-dwc3
20 - qcom,ipq6018-dwc3
21 - qcom,ipq8064-dwc3
22 - qcom,ipq8074-dwc3
23 - qcom,ipq9574-dwc3
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| D | rockchip,dwc3.yaml | 4 $id: http://devicetree.org/schemas/usb/rockchip,dwc3.yaml#
7 title: Rockchip SuperSpeed DWC3 USB SoC controller
13 The common content of the node is defined in snps,dwc3.yaml.
28 - rockchip,rk3328-dwc3
29 - rockchip,rk3568-dwc3
30 - rockchip,rk3576-dwc3
31 - rockchip,rk3588-dwc3
39 - rockchip,rk3328-dwc3
40 - rockchip,rk3568-dwc3
41 - rockchip,rk3576-dwc3
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| D | realtek,rtd-dwc3.yaml | 5 $id: http://devicetree.org/schemas/usb/realtek,rtd-dwc3.yaml#
8 title: Realtek DWC3 USB SoC Controller Glue
14 The Realtek DHC SoC embeds a DWC3 USB IP Core configured for USB 2.0
21 - realtek,rtd1295-dwc3
22 - realtek,rtd1315e-dwc3
23 - realtek,rtd1319-dwc3
24 - realtek,rtd1319d-dwc3
25 - realtek,rtd1395-dwc3
26 - realtek,rtd1619-dwc3
27 - realtek,rtd1619b-dwc3
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| D | dwc3-st.txt | 1 ST DWC3 glue logic
3 This file documents the parameters for the dwc3-st driver.
4 This driver controls the glue logic used to configure the dwc3 core on
8 - compatible : must be "st,stih407-dwc3"
32 The dwc3 core should be added as subnode to ST DWC3 glue as shown in the
33 example below. The DT binding details of dwc3 can be found in:
34 Documentation/devicetree/bindings/usb/snps,dwc3.yaml
37 is "otg", which isn't supported by this SoC. Valid dr_mode values for dwc3-st are either "host"
44 st_dwc3: dwc3@8f94000 {
45 compatible = "st,stih407-dwc3";
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| D | omap-usb.txt | 46 OMAP DWC3 GLUE
48 * "ti,dwc3" for OMAP5 and DRA7
49 * "ti,am437x-dwc3" for AM437x
60 - extcon : phandle for the extcon device omap dwc3 uses to detect
65 The dwc3 core should be added as subnode to omap dwc3 glue.
66 - dwc3 :
67 The binding details of dwc3 can be found in:
68 Documentation/devicetree/bindings/usb/snps,dwc3.yaml
71 compatible = "ti,dwc3";
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| D | snps,dwc3.yaml | 4 $id: http://devicetree.org/schemas/usb/snps,dwc3.yaml#
13 This is usually a subnode to DWC3 glue to which it is connected, but can also
18 - $ref: snps,dwc3-common.yaml#
24 - const: snps,dwc3
25 - const: synopsys,dwc3
33 It's either a single common DWC3 interrupt (dwc_usb3) or individual
67 The DWC3 has 2 power-domains. The power management unit (PMU) and
88 compatible = "snps,dwc3";
96 compatible = "snps,dwc3";
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| D | fsl,ls1028a.yaml | 7 title: Freescale layerscape SuperSpeed DWC3 USB SoC controller
17 - fsl,ls1028a-dwc3
25 - fsl,ls1028a-dwc3
26 - const: snps,dwc3
42 - $ref: snps,dwc3.yaml#
49 compatible = "fsl,ls1028a-dwc3", "snps,dwc3";
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| D | fsl,imx8mq-dwc3.yaml | 4 $id: http://devicetree.org/schemas/usb/fsl,imx8mq-dwc3.yaml#
18 - fsl,imx8mq-dwc3
25 - const: fsl,imx8mq-dwc3
26 - const: snps,dwc3
29 - $ref: snps,dwc3.yaml#
39 compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
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| D | ti,keystone-dwc3.yaml | 4 $id: http://devicetree.org/schemas/usb/ti,keystone-dwc3.yaml#
16 - ti,keystone-dwc3
17 - ti,am654-dwc3
61 $ref: snps,dwc3.yaml#
77 dwc3@2680000 {
78 compatible = "ti,keystone-dwc3";
87 compatible = "snps,dwc3";
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| D | fsl,imx8mp-dwc3.yaml | 5 $id: http://devicetree.org/schemas/usb/fsl,imx8mp-dwc3.yaml#
17 - const: fsl,imx95-dwc3
18 - const: fsl,imx8mp-dwc3
19 - const: fsl,imx8mp-dwc3
24 - description: Address and length of the register set for the wrapper of dwc3 core on the SOC.
85 $ref: snps,dwc3.yaml#
107 compatible = "fsl,imx8mp-dwc3";
121 compatible = "snps,dwc3";
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| D | intel,keembay-dwc3.yaml | 4 $id: http://devicetree.org/schemas/usb/intel,keembay-dwc3.yaml#
7 title: Intel Keem Bay DWC3 USB controller
14 const: intel,keembay-dwc3
41 $ref: snps,dwc3.yaml#
61 compatible = "intel,keembay-dwc3";
72 compatible = "snps,dwc3";
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| D | dwc3-xilinx.yaml | 4 $id: http://devicetree.org/schemas/usb/dwc3-xilinx.yaml#
7 title: Xilinx SuperSpeed DWC3 USB SoC controller
17 - xlnx,zynqmp-dwc3
18 - xlnx,versal-dwc3
83 $ref: snps,dwc3.yaml#
114 compatible = "xlnx,zynqmp-dwc3";
128 compatible = "snps,dwc3";
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| /linux-6.14.4/drivers/usb/dwc3/ |
| D | Makefile | 5 obj-$(CONFIG_USB_DWC3) += dwc3.o
7 dwc3-y := core.o
10 dwc3-y += trace.o
14 dwc3-y += host.o
18 dwc3-y += gadget.o ep0.o
22 dwc3-y += drd.o
26 dwc3-y += ulpi.o
30 dwc3-y += debugfs.o
45 obj-$(CONFIG_USB_DWC3_AM62) += dwc3-am62.o
46 obj-$(CONFIG_USB_DWC3_OMAP) += dwc3-omap.o
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| D | dwc3-haps.c | 3 * dwc3-haps.c - Synopsys HAPS PCI Specific glue layer
20 * @dwc3: child dwc3 platform_device
24 struct platform_device *dwc3; member
60 dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO); in dwc3_haps_probe()
61 if (!dwc->dwc3) in dwc3_haps_probe()
75 ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res)); in dwc3_haps_probe()
77 dev_err(dev, "couldn't add resources to dwc3 device\n"); in dwc3_haps_probe()
82 dwc->dwc3->dev.parent = dev; in dwc3_haps_probe()
84 ret = device_add_software_node(&dwc->dwc3->dev, &dwc3_haps_swnode); in dwc3_haps_probe()
88 ret = platform_device_add(dwc->dwc3); in dwc3_haps_probe()
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| D | dwc3-imx8mp.c | 3 * dwc3-imx8mp.c - NXP imx8mp Specific Glue layer
54 struct platform_device *dwc3; member
103 struct dwc3 *dwc3 = platform_get_drvdata(dwc3_imx->dwc3); in dwc3_imx8mp_wakeup_enable() local
106 if (!dwc3) in dwc3_imx8mp_wakeup_enable()
111 if ((dwc3->current_dr_role == DWC3_GCTL_PRTCAP_HOST) && dwc3->xhci) { in dwc3_imx8mp_wakeup_enable()
145 struct dwc3 *dwc = platform_get_drvdata(dwc3_imx->dwc3); in dwc3_imx8mp_interrupt()
211 "snps,dwc3"); in dwc3_imx8mp_probe()
213 return dev_err_probe(dev, -ENODEV, "failed to find dwc3 core child\n"); in dwc3_imx8mp_probe()
232 dev_err(&pdev->dev, "failed to create dwc3 core\n"); in dwc3_imx8mp_probe()
236 dwc3_imx->dwc3 = of_find_device_by_node(dwc3_np); in dwc3_imx8mp_probe()
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| D | dwc3-pci.c | 3 * dwc3-pci.c - PCI Specific glue layer
74 * @dwc3: child dwc3 platform_device
81 struct platform_device *dwc3; member
273 * Make the pdev name predictable (only 1 DWC3 on BYT) in dwc3_pci_quirks()
277 dwc->dwc3->id = PLATFORM_DEVID_NONE; in dwc3_pci_quirks()
278 platform_bytcr_gpios.dev_id = "dwc3.ulpi"; in dwc3_pci_quirks()
298 return device_add_software_node(&dwc->dwc3->dev, swnode); in dwc3_pci_quirks()
305 struct platform_device *dwc3 = dwc->dwc3; in dwc3_pci_resume_work() local
308 ret = pm_runtime_get_sync(&dwc3->dev); in dwc3_pci_resume_work()
310 pm_runtime_put_sync_autosuspend(&dwc3->dev); in dwc3_pci_resume_work()
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| D | drd.c | 19 static void dwc3_otg_disable_events(struct dwc3 *dwc, u32 disable_mask) in dwc3_otg_disable_events()
27 static void dwc3_otg_enable_events(struct dwc3 *dwc, u32 enable_mask) in dwc3_otg_enable_events()
35 static void dwc3_otg_clear_events(struct dwc3 *dwc) in dwc3_otg_clear_events()
54 struct dwc3 *dwc = _dwc; in dwc3_otg_thread_irq()
72 struct dwc3 *dwc = _dwc; in dwc3_otg_irq()
93 static void dwc3_otgregs_init(struct dwc3 *dwc) in dwc3_otgregs_init()
137 static int dwc3_otg_get_irq(struct dwc3 *dwc) in dwc3_otg_get_irq()
167 void dwc3_otg_init(struct dwc3 *dwc) in dwc3_otg_init()
186 void dwc3_otg_exit(struct dwc3 *dwc) in dwc3_otg_exit()
195 void dwc3_otg_host_init(struct dwc3 *dwc) in dwc3_otg_host_init()
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| D | core.c | 50 static int dwc3_get_dr_mode(struct dwc3 *dwc) in dwc3_get_dr_mode()
93 !DWC3_VER_IS_PRIOR(DWC3, 330A)) in dwc3_get_dr_mode()
108 void dwc3_enable_susphy(struct dwc3 *dwc, bool enable) in dwc3_enable_susphy()
134 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode, bool ignore_susphy) in dwc3_set_prtcap()
161 struct dwc3 *dwc = work_to_dwc(work); in __dwc3_set_mode()
210 if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) || in __dwc3_set_mode()
285 void dwc3_set_mode(struct dwc3 *dwc, u32 mode) in dwc3_set_mode()
301 struct dwc3 *dwc = dep->dwc; in dwc3_core_fifo_space()
317 int dwc3_core_soft_reset(struct dwc3 *dwc) in dwc3_core_soft_reset()
324 * XHCI driver will reset the host block. If dwc3 was configured for in dwc3_core_soft_reset()
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| D | ep0.c | 30 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
31 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
33 static int dwc3_ep0_delegate_req(struct dwc3 *dwc,
40 struct dwc3 *dwc; in dwc3_ep0_prepare_one_trb()
68 struct dwc3 *dwc; in dwc3_ep0_start_trans()
92 struct dwc3 *dwc = dep->dwc; in __dwc3_gadget_ep0_queue()
195 struct dwc3 *dwc = dep->dwc; in dwc3_gadget_ep0_queue()
223 void dwc3_ep0_stall_and_restart(struct dwc3 *dwc) in dwc3_ep0_stall_and_restart()
258 struct dwc3 *dwc = dep->dwc; in __dwc3_gadget_ep0_set_halt()
268 struct dwc3 *dwc = dep->dwc; in dwc3_gadget_ep0_set_halt()
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| D | gadget.c | 41 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) in dwc3_gadget_set_test_mode()
72 int dwc3_gadget_get_link_state(struct dwc3 *dwc) in dwc3_gadget_get_link_state()
89 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state) in dwc3_gadget_set_link_state()
98 if (!DWC3_VER_IS_PRIOR(DWC3, 194A)) { in dwc3_gadget_set_link_state()
125 if (!DWC3_VER_IS_PRIOR(DWC3, 194A)) in dwc3_gadget_set_link_state()
142 static void dwc3_ep0_reset_state(struct dwc3 *dwc) in dwc3_ep0_reset_state()
196 struct dwc3 *dwc = dep->dwc; in dwc3_gadget_del_and_unmap_request()
229 struct dwc3 *dwc = dep->dwc; in dwc3_gadget_giveback()
248 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd, in dwc3_send_gadget_generic_command()
279 static int __dwc3_gadget_wakeup(struct dwc3 *dwc, bool async);
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| D | core.h | 37 * DWC3 Multiport controllers support up to 15 High-Speed PHYs
84 /* DWC3 registers memory space boundaries */
706 struct dwc3 *dwc;
756 struct dwc3 *dwc;
951 * @status: internal dwc3 request status tracking
996 * struct dwc3 - representation of our controller
1092 * @sysdev_is_parent: true when dwc3 device has a parent driver
1100 * @do_fifo_resize: true when txfifo resizing is enabled for dwc3 endpoints
1168 struct dwc3 { struct
1402 #define work_to_dwc(w) (container_of((w), struct dwc3, drd_work)) argument
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| D | dwc3-of-simple.c | 3 * dwc3-of-simple.c - OF glue layer for simple integrations
9 * This is a combination of the old dwc3-qcom.c by Ivan T. Ivanov
52 if (of_device_is_compatible(np, "rockchip,rk3399-dwc3")) in dwc3_of_simple_probe()
171 { .compatible = "rockchip,rk3399-dwc3" },
172 { .compatible = "sprd,sc9860-dwc3" },
173 { .compatible = "allwinner,sun50i-h6-dwc3" },
174 { .compatible = "hisilicon,hi3670-dwc3" },
175 { .compatible = "hisilicon,hi3798mv200-dwc3" },
176 { .compatible = "intel,keembay-dwc3" },
186 .name = "dwc3-of-simple",
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| D | gadget.h | 18 struct dwc3;
93 * @reason: cancelled reason for the dwc3 request
110 void dwc3_ep0_interrupt(struct dwc3 *dwc,
112 void dwc3_ep0_out_start(struct dwc3 *dwc);
113 void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep);
114 void dwc3_ep0_stall_and_restart(struct dwc3 *dwc);
120 void dwc3_ep0_send_delayed_status(struct dwc3 *dwc);
122 int dwc3_gadget_start_config(struct dwc3 *dwc, unsigned int resource_index);
126 * @dep: dwc3 endpoint
147 static inline void dwc3_gadget_dctl_write_safe(struct dwc3 *dwc, u32 value) in dwc3_gadget_dctl_write_safe()
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| D | dwc3-qcom.c | 4 * Inspired by dwc3-of-simple.c
76 struct platform_device *dwc3; member
263 max_speed = usb_get_maximum_speed(&qcom->dwc3->dev); in dwc3_qcom_interconnect_init()
306 struct dwc3 *dwc; in dwc3_qcom_is_host()
311 dwc = platform_get_drvdata(qcom->dwc3); in dwc3_qcom_is_host()
322 struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3); in dwc3_qcom_read_usb2_speed()
501 struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3); in qcom_dwc3_resume_irq()
519 /* Configure dwc3 to use UTMI clock as PIPE clock not present */ in dwc3_qcom_select_utmi_clk()
711 "snps,dwc3"); in dwc3_qcom_of_register_core()
713 dev_err(dev, "failed to find dwc3 core child\n"); in dwc3_qcom_of_register_core()
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| /linux-6.14.4/Documentation/devicetree/bindings/soc/socionext/ |
| D | socionext,uniphier-dwc3-glue.yaml | 4 $id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-dwc3-glue.yaml#
7 title: Socionext UniPhier SoC DWC3 USB3.0 glue layer
13 DWC3 USB3.0 glue layer implemented on Socionext UniPhier SoCs is
14 a sideband logic handling signals to DWC3 host controller inside
21 - socionext,uniphier-pro4-dwc3-glue
22 - socionext,uniphier-pro5-dwc3-glue
23 - socionext,uniphier-pxs2-dwc3-glue
24 - socionext,uniphier-ld20-dwc3-glue
25 - socionext,uniphier-pxs3-dwc3-glue
26 - socionext,uniphier-nx1-dwc3-glue
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