| /linux-6.14.4/drivers/pci/controller/dwc/ |
| D | pcie-rcar-gen4.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * PCIe controller driver for Renesas R-Car Gen4 Series SoCs
4 * Copyright (C) 2022-2023 Renesas Electronics Corporation
6 * The r8a779g0 (R-Car V4H) controller requires a specific firmware to be
7 * provided, to initialize the PHY. Otherwise, the PCIe controller will not
24 #include "pcie-designware.h"
26 /* Renesas-specific */
27 /* PCIe Mode Setting Register 0 */
34 /* PCIe Interrupt Status 0 */
37 /* PCIe Interrupt Status 0 Enable */
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| D | pcie-designware-plat.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe RC driver for Synopsys DesignWare Core
5 * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
21 #include "pcie-designware.h"
35 static void dw_plat_pcie_ep_init(struct dw_pcie_ep *ep) in dw_plat_pcie_ep_init() argument
37 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); in dw_plat_pcie_ep_init()
44 static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, in dw_plat_pcie_ep_raise_irq() argument
47 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); in dw_plat_pcie_ep_raise_irq()
51 return dw_pcie_ep_raise_intx_irq(ep, func_no); in dw_plat_pcie_ep_raise_irq()
53 return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); in dw_plat_pcie_ep_raise_irq()
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| D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PCIE_DW) += pcie-designware.o
3 obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o
4 obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o
5 obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
6 obj-$(CONFIG_PCIE_BT1) += pcie-bt1.o
7 obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
8 obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
9 obj-$(CONFIG_PCIE_FU740) += pcie-fu740.o
10 obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
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| D | pcie-designware.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Synopsys DesignWare PCIe host controller driver
17 #include <linux/dma-mapping.h>
25 #include <linux/pci-epc.h>
26 #include <linux/pci-epf.h>
28 /* DWC PCIe IP-core versions (native support since v4.70a) */
38 ((_pci)->version _op DW_PCIE_VER_ ## _ver)
52 /* DWC PCIe controller capabilities */
58 test_bit(DW_PCIE_CAP_ ## _cap, &(_pci)->caps)
61 set_bit(DW_PCIE_CAP_ ## _cap, &(_pci)->caps)
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| D | pcie-dw-rockchip.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Rockchip SoCs.
6 * http://www.rock-chips.com
8 * Author: Simon Xue <xxm@rock-chips.com>
24 #include "pcie-designware.h"
34 #define to_rockchip_pcie(x) dev_get_drvdata((x)->dev)
77 return readl_relaxed(rockchip->apb_base + reg); in rockchip_pcie_readl_apb()
83 writel_relaxed(val, rockchip->apb_base + reg); in rockchip_pcie_writel_apb()
97 generic_handle_domain_irq(rockchip->irq_domain, hwirq); in rockchip_pcie_intx_handler()
105 HIWORD_UPDATE_BIT(BIT(data->hwirq)), in rockchip_intx_mask()
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| /linux-6.14.4/Documentation/devicetree/bindings/pci/ |
| D | axis,artpec6-pcie.txt | 1 * Axis ARTPEC-6 PCIe interface
3 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
4 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
7 - compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode;
8 "axis,artpec6-pcie-ep", "snps,dw-pcie" for ARTPEC-6 in EP mode;
9 "axis,artpec7-pcie", "snps,dw-pcie" for ARTPEC-7 in RC mode;
10 "axis,artpec7-pcie-ep", "snps,dw-pcie" for ARTPEC-7 in EP mode;
11 - reg: base addresses and lengths of the PCIe controller (DBI),
13 - reg-names: Must include the following entries:
14 - "dbi"
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| D | rockchip-dw-pcie-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DesignWare based PCIe Endpoint controller on Rockchip SoCs
10 - Niklas Cassel <[email protected]>
13 RK3588 SoC PCIe Endpoint controller is based on the Synopsys DesignWare
14 PCIe IP and thus inherits all the common properties defined in
15 snps,dw-pcie-ep.yaml.
18 - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
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| D | fsl,imx6q-pcie-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX6 PCIe Endpoint controller
10 - Lucas Stach <[email protected]>
11 - Richard Zhu <[email protected]>
14 This PCIe controller is based on the Synopsys DesignWare PCIe IP and
15 thus inherits all the common properties defined in snps,dw-pcie-ep.yaml.
22 - fsl,imx8mm-pcie-ep
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| D | socionext,uniphier-pcie-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier PCIe endpoint controller
10 UniPhier PCIe endpoint controller is based on the Synopsys DesignWare
11 PCI core. It shares common features with the PCIe DesignWare core and
13 Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml.
16 - Kunihiko Hayashi <[email protected]>
21 - socionext,uniphier-pro5-pcie-ep
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| D | snps,dw-pcie-ep.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare PCIe endpoint interface
10 - Jingoo Han <[email protected]>
11 - Gustavo Pimentel <[email protected]>
14 Synopsys DesignWare PCIe host controller endpoint
16 # Please create a separate DT-schema for your DWC PCIe Endpoint controller
17 # and make sure it's assigned with the vendor-specific compatible string.
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| D | ti-pci.txt | 3 PCIe DesignWare Controller
4 - compatible: Should be "ti,dra7-pcie" for RC (deprecated)
5 Should be "ti,dra7-pcie-ep" for EP (deprecated)
6 Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode
7 Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode
8 Should be "ti,dra726-pcie-rc" for dra72x in RC mode
9 Should be "ti,dra726-pcie-ep" for dra72x in EP mode
10 - phys : list of PHY specifiers (used by generic PHY framework)
11 - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
13 - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
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| D | rcar-gen4-pci-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2022-2023 Renesas Electronics Corp.
4 ---
5 $id: http://devicetree.org/schemas/pci/rcar-gen4-pci-ep.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Renesas R-Car Gen4 PCIe Endpoint
11 - Yoshihiro Shimoda <[email protected]>
14 - $ref: snps,dw-pcie-ep.yaml#
19 - enum:
20 - renesas,r8a779f0-pcie-ep # R-Car S4-8
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| D | fsl,imx6q-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX6 PCIe host controller
10 - Lucas Stach <[email protected]>
11 - Richard Zhu <[email protected]>
14 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
15 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
19 See fsl,imx6q-pcie-ep.yaml for details on the Endpoint mode device tree
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| D | nvidia,tegra194-pcie-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra194 (and later) PCIe Endpoint controller (Synopsys DesignWare Core based)
10 - Thierry Reding <[email protected]>
11 - Jon Hunter <[email protected]>
12 - Vidya Sagar <[email protected]>
15 This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus
16 inherits all the common properties defined in snps,dw-pcie-ep.yaml. Some
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| D | rockchip-dw-pcie-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DesignWare based PCIe RC/EP controller on Rockchip SoCs
10 - Shawn Lin <shawn.lin@rock-chips.com>
11 - Simon Xue <xxm@rock-chips.com>
12 - Heiko Stuebner <[email protected]>
15 Generic properties for the DesignWare based PCIe RC/EP controller on Rockchip
22 - description: AHB clock for PCIe master
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| D | nvidia,tegra194-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra194 (and later) PCIe controller (Synopsys DesignWare Core based)
10 - Thierry Reding <[email protected]>
11 - Jon Hunter <[email protected]>
12 - Vidya Sagar <[email protected]>
15 This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus
16 inherits all the common properties defined in snps,dw-pcie.yaml. Some of
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| D | snps,dw-pcie-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DWC PCIe RP/EP controller
10 - Jingoo Han <[email protected]>
11 - Gustavo Pimentel <[email protected]>
14 Generic Synopsys DesignWare PCIe Root Port and Endpoint controller
22 DWC PCIe CSR space is normally accessed over the dedicated Data Bus
23 Interface - DBI. In accordance with the reference manual the register
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| /linux-6.14.4/include/linux/dma/ |
| D | edma.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
30 * struct dw_edma_core_ops - platform-specific eDMA methods
32 * method accepts the channel id in the end-to-end
35 * @pci_address: Get PCIe bus address corresponding to the passed CPU
38 * the DW PCIe RP/EP controller with the DW eDMA device in
56 * enum dw_edma_chip_flags - Flags specific to an eDMA chip
64 * struct dw_edma_chip - representation of DesignWare eDMA controller hardware
79 * @dw: struct dw_edma that is filled by dw_edma_probe()
101 struct dw_edma *dw; member
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| /linux-6.14.4/drivers/pci/controller/ |
| D | pcie-altera.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright Altera Corporation (C) 2013-2015. All rights reserved
6 * Description: Altera PCIe host controller driver
44 #define S10_RP_CFG_ADDR(pcie, reg) \ argument
45 (((pcie)->hip_base) + (reg) + (1 << 20))
46 #define S10_RP_SECONDARY(pcie) \ argument
47 readb(S10_RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
58 #define TLP_CFG_DW0(pcie, cfg) \ argument
61 #define TLP_CFG_DW1(pcie, tag, be) \ argument
62 (((PCI_DEVID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
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| /linux-6.14.4/drivers/dma/dw-edma/ |
| D | dw-edma-core.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
17 #include <linux/dma-mapping.h>
19 #include "dw-edma-core.h"
20 #include "dw-edma-v0-core.h"
21 #include "dw-hdma-v0-core.h"
23 #include "../virt-dma.h"
28 return &dchan->dev->device; in dchan2dev()
34 return &chan->vc.chan.dev->device; in chan2dev()
46 struct dw_edma_chip *chip = chan->dw->chip; in dw_edma_get_pci_address()
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| D | dw-hdma-v0-core.c | 1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/io-64-nonatomic-lo-hi.h>
11 #include "dw-edma-core.h"
12 #include "dw-hdma-v0-core.h"
13 #include "dw-hdma-v0-regs.h"
14 #include "dw-hdma-v0-debugfs.h"
26 static inline struct dw_hdma_v0_regs __iomem *__dw_regs(struct dw_edma *dw) in __dw_regs() argument
28 return dw->chip->reg_base; in __dw_regs()
32 __dw_ch_regs(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch) in __dw_ch_regs() argument
35 return &(__dw_regs(dw)->ch[ch].wr); in __dw_ch_regs()
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| D | dw-edma-v0-core.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
11 #include <linux/io-64-nonatomic-lo-hi.h>
13 #include "dw-edma-core.h"
14 #include "dw-edma-v0-core.h"
15 #include "dw-edma-v0-regs.h"
16 #include "dw-edma-v0-debugfs.h"
28 static inline struct dw_edma_v0_regs __iomem *__dw_regs(struct dw_edma *dw) in __dw_regs() argument
30 return dw->chip->reg_base; in __dw_regs()
33 #define SET_32(dw, name, value) \ argument
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| /linux-6.14.4/arch/arm/boot/dts/axis/ |
| D | artpec6.dtsi | 2 * Device Tree Source for the Axis ARTPEC-6 SoC
4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/dma/nbpfaxi.h>
45 #include <dt-bindings/clock/axis,artpec6-clkctrl.h>
48 #address-cells = <1>;
49 #size-cells = <1>;
51 interrupt-parent = <&intc>;
54 #address-cells = <1>;
55 #size-cells = <0>;
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| /linux-6.14.4/arch/arm64/boot/dts/rockchip/ |
| D | rk3399-base.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3399-power.h>
12 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
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| /linux-6.14.4/drivers/scsi/mpt3sas/ |
| D | mpt3sas_base.c | 6 * Copyright (C) 2012-2014 LSI Corporation
7 * Copyright (C) 2013-2014 Avago Technologies
8 * (mailto: MPT-[email protected])
23 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
42 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
57 #include <linux/dma-mapping.h>
75 static int max_queue_depth = -1;
79 static int max_sgl_entries = -1;
83 static int msix_disable = -1;
91 static int max_msix_vectors = -1;
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