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/linux-6.14.4/drivers/phy/cadence/
Dcdns-dphy.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright: 2017-2018 Cadence Design Systems, Inc.
17 #include <linux/phy/phy-mipi-dphy.h>
23 /* DPHY registers */
94 int (*probe)(struct cdns_dphy *dphy);
95 void (*remove)(struct cdns_dphy *dphy);
96 void (*set_psm_div)(struct cdns_dphy *dphy, u8 div);
97 void (*set_clk_lane_cfg)(struct cdns_dphy *dphy,
98 enum cdns_dphy_clk_lane_cfg cfg);
99 void (*set_pll_cfg)(struct cdns_dphy *dphy,
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/linux-6.14.4/Documentation/devicetree/bindings/phy/
Drockchip-mipi-dphy-rx0.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip-mipi-dphy-rx0.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC MIPI RX0 D-PHY
10 - Helen Koike <[email protected]>
11 - Ezequiel Garcia <[email protected]>
14 The Rockchip SoC has a MIPI D-PHY bus with an RX0 entry which connects to
19 const: rockchip,rk3399-mipi-dphy-rx0
23 - description: MIPI D-PHY ref clock
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Dstarfive,jh7110-dphy-rx.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/starfive,jh7110-dphy-rx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive SoC JH7110 MIPI D-PHY Rx Controller
10 - Jack Zhu <[email protected]>
11 - Changhuang Liang <[email protected]>
14 StarFive SoCs contain a MIPI CSI D-PHY based on M31 IP, used to
19 const: starfive,jh7110-dphy-rx
26 - description: config clock
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/linux-6.14.4/drivers/phy/freescale/
Dphy-fsl-imx8-mipi-dphy.c1 // SPDX-License-Identifier: GPL-2.0+
9 #include <linux/clk-provider.h>
22 #include <dt-bindings/firmware/imx/rsrc.h>
35 /* DPHY registers */
63 ((x) < 32) ? 0xe0 | ((x) - 16) : \
64 ((x) < 64) ? 0xc0 | ((x) - 32) : \
65 ((x) < 128) ? 0x80 | ((x) - 64) : \
66 ((x) - 128))
67 #define CN(x) (((x) == 1) ? 0x1f : (((CN_BUF) >> ((x) - 1)) & 0x1f))
68 #define CO(x) ((CO_BUF) >> (8 - (x)) & 0x03)
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/linux-6.14.4/drivers/gpu/drm/bridge/imx/
Dimx93-mipi-dsi.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <linux/media-bus-format.h>
17 #include <linux/phy/phy-mipi-dphy.h>
26 /* DPHY PLL configuration registers */
42 #define M(x) FIELD_PREP(M_MASK, ((x) - 2))
44 #define N(x) FIELD_PREP(N_MASK, ((x) - 1))
121 /* DPHY Databook Table 3-13 Charge-pump Programmability */
136 /* DPHY Databook Table 5-7 Frequency Ranges and Defaults */
207 ret = regmap_write(dsi->regmap, reg, value); in dphy_pll_write()
209 dev_err(dsi->dev, "failed to write 0x%08x to pll reg 0x%x: %d\n", in dphy_pll_write()
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/linux-6.14.4/drivers/phy/starfive/
Dphy-jh7110-dphy-rx.c1 // SPDX-License-Identifier: GPL-2.0+
3 * StarFive JH7110 DPHY RX driver
75 struct stf_dphy *dphy = phy_get_drvdata(phy); in stf_dphy_configure() local
76 const struct stf_dphy_info *info = dphy->info; in stf_dphy_configure()
84 FIELD_PREP(STF_DPHY_LANE_SWAP_CLK, info->maps[0]) | in stf_dphy_configure()
85 FIELD_PREP(STF_DPHY_LANE_SWAP_CLK1, info->maps[5]) | in stf_dphy_configure()
86 FIELD_PREP(STF_DPHY_LANE_SWAP_LAN0, info->maps[1]) | in stf_dphy_configure()
87 FIELD_PREP(STF_DPHY_LANE_SWAP_LAN1, info->maps[2]), in stf_dphy_configure()
88 dphy->regs + STF_DPHY_APBCFGSAIF_SYSCFG(188)); in stf_dphy_configure()
90 writel(FIELD_PREP(STF_DPHY_LANE_SWAP_LAN2, info->maps[3]) | in stf_dphy_configure()
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/linux-6.14.4/drivers/gpu/drm/kmb/
Dkmb_dsi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2019-2020 Intel Corporation
178 clk_disable_unprepare(kmb_dsi->clk_mipi); in kmb_dsi_clk_disable()
179 clk_disable_unprepare(kmb_dsi->clk_mipi_ecfg); in kmb_dsi_clk_disable()
180 clk_disable_unprepare(kmb_dsi->clk_mipi_cfg); in kmb_dsi_clk_disable()
186 mipi_dsi_host_unregister(kmb_dsi->host); in kmb_dsi_host_unregister()
225 return -ENOMEM; in kmb_dsi_host_bridge_init()
227 dsi_host->ops = &kmb_dsi_host_ops; in kmb_dsi_host_bridge_init()
233 return -ENOMEM; in kmb_dsi_host_bridge_init()
237 dsi_host->dev = dev; in kmb_dsi_host_bridge_init()
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Dkmb_dsi.h1 /* SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2019-2020 Intel Corporation
12 /* MIPI TX CFG */
18 /* DPHY Tx test codes*/
43 /* DPHY params */
58 /* 2 Data Lanes per D-PHY */
81 /* DPHY Tx test codes */
341 writel(value, (kmb_dsi->mipi_mmio + reg)); in kmb_write_mipi()
346 return readl(kmb_dsi->mipi_mmio + reg); in kmb_read_mipi()
354 u32 mask = (1 << num_bits) - 1; in kmb_write_bits_mipi()
/linux-6.14.4/drivers/media/platform/rockchip/rkisp1/
Drkisp1-csi.c1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Rockchip ISP1 Driver - CSI-2 Receiver
16 #include <linux/phy/phy-mipi-dphy.h>
18 #include <media/v4l2-ctrls.h>
19 #include <media/v4l2-fwnode.h>
21 #include "rkisp1-common.h"
22 #include "rkisp1-csi.h"
37 struct rkisp1_csi *csi = &rkisp1->csi; in rkisp1_csi_link_sensor()
40 s_asd->pixel_rate_ctrl = v4l2_ctrl_find(sd->ctrl_handler, in rkisp1_csi_link_sensor()
42 if (!s_asd->pixel_rate_ctrl) { in rkisp1_csi_link_sensor()
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Drkisp1-common.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
3 * Rockchip ISP1 Driver - Common definitions
17 #include <linux/rkisp1-config.h>
18 #include <media/media-device.h>
19 #include <media/media-entity.h>
20 #include <media/v4l2-ctrls.h>
21 #include <media/v4l2-device.h>
22 #include <media/videobuf2-v4l2.h>
24 #include "rkisp1-regs.h"
38 * model-specific and stored in the rkisp1_info structure.
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/linux-6.14.4/drivers/media/platform/cadence/
Dcdns-csi2rx.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for Cadence MIPI-CSI2 RX Controller v1.3
20 #include <media/v4l2-ctrls.h>
21 #include <media/v4l2-device.h>
22 #include <media/v4l2-fwnode.h>
23 #include <media/v4l2-subdev.h>
91 struct phy *dphy; member
150 csi2rx->base + CSI2RX_SOFT_RESET_REG); in csi2rx_reset()
152 for (i = 0; i < csi2rx->max_streams; i++) { in csi2rx_reset()
154 csi2rx->base + CSI2RX_STREAM_CTRL_REG(i)); in csi2rx_reset()
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/linux-6.14.4/drivers/phy/rockchip/
Dphy-rockchip-inno-dsidphy.c1 // SPDX-License-Identifier: GPL-2.0
5 * Author: Wyon Bi <bivvy.bi@rock-chips.com>
12 #include <linux/clk-provider.h>
24 #include <linux/phy/phy-mipi-dphy.h>
290 orig = readl(inno->phy_base + reg); in phy_update_bits()
293 writel(tmp, inno->phy_base + reg); in phy_update_bits()
299 unsigned long prate = clk_get_rate(inno->ref_clk); in inno_dsidphy_pll_calc_rate()
310 * PLL_Output_Frequency: it is equal to DDR-Clock-Frequency * 2 in inno_dsidphy_pll_calc_rate()
343 delta = abs(fout - tmp); in inno_dsidphy_pll_calc_rate()
358 inno->pll.prediv = best_prediv; in inno_dsidphy_pll_calc_rate()
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Dphy-rockchip-dphy-rx0.c1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Rockchip MIPI Synopsys DPHY RX0 driver
11 * chromeos-4.4 branch.
14 * Jacob Chen <jacob2.chen@rock-chips.com>
15 * Shunqian Zheng <zhengsq@rock-chips.com>
25 #include <linux/phy/phy-mipi-dphy.h>
64 "dphy-ref",
65 "dphy-cfg",
110 { .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, }
162 const struct dphy_reg *reg = &priv->drv_data->regs[index]; in rk_dphy_write_grf()
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/linux-6.14.4/Documentation/devicetree/bindings/soc/rockchip/
Dgrf.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <[email protected]>
15 - items:
16 - enum:
17 - rockchip,rk3288-sgrf
18 - rockchip,rk3566-pipe-grf
19 - rockchip,rk3568-pcie3-phy-grf
20 - rockchip,rk3568-pipe-grf
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/linux-6.14.4/drivers/phy/
Dphy-core-mipi-dphy.c1 /* SPDX-License-Identifier: GPL-2.0 */
13 #include <linux/phy/phy-mipi-dphy.h>
16 * Minimum D-PHY timings based on MIPI D-PHY specification. Derived
18 * of the D-PHY specification (v1.2).
24 struct phy_configure_opts_mipi_dphy *cfg) in phy_mipi_dphy_calc_config() argument
28 if (!cfg) in phy_mipi_dphy_calc_config()
29 return -EINVAL; in phy_mipi_dphy_calc_config()
39 cfg->clk_miss = 0; in phy_mipi_dphy_calc_config()
40 cfg->clk_post = 60000 + 52 * ui; in phy_mipi_dphy_calc_config()
41 cfg->clk_pre = 8; in phy_mipi_dphy_calc_config()
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/linux-6.14.4/drivers/gpu/drm/bridge/
Dnwl-dsi.c1 // SPDX-License-Identifier: GPL-2.0+
15 #include <linux/media-bus-format.h>
34 #include "nwl-dsi.h"
36 #define DRV_NAME "nwl-dsi"
79 * 2. Configure DSI Host and DPHY and enable DPHY
130 int ret = dsi->error; in nwl_dsi_clear_error()
132 dsi->error = 0; in nwl_dsi_clear_error()
140 if (dsi->error) in nwl_dsi_write()
143 ret = regmap_write(dsi->regmap, reg, val); in nwl_dsi_write()
145 DRM_DEV_ERROR(dsi->dev, in nwl_dsi_write()
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/linux-6.14.4/drivers/media/pci/intel/ipu6/
Dipu6-isys-dwc-phy.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013--2024 Intel Corporation
13 #include "ipu6-bus.h"
14 #include "ipu6-isys.h"
15 #include "ipu6-platform-isys-csi2-reg.h"
31 * - req: 0 for read, 1 for write
32 * - 12 bits address
33 * - 8bits data (will ignore for read)
34 * --24----16------4-----0
35 * --|-data-|-addr-|-req-|
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Dipu6-isys-csi2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013--2024 Intel Corporation
16 #include <media/media-entity.h>
17 #include <media/v4l2-ctrls.h>
18 #include <media/v4l2-device.h>
19 #include <media/v4l2-event.h>
20 #include <media/v4l2-subdev.h>
22 #include "ipu6-bus.h"
23 #include "ipu6-isys.h"
24 #include "ipu6-isys-csi2.h"
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Dipu6-isys-mcd-phy.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013--2024 Intel Corporation
14 #include <media/v4l2-async.h>
17 #include "ipu6-bus.h"
18 #include "ipu6-isys.h"
19 #include "ipu6-isys-csi2.h"
20 #include "ipu6-platform-isys-csi2-reg.h"
38 * There are 2 MCD DPHY instances on TGL and 1 MCD DPHY instance on ADL.
39 * Each MCD PHY has 12-lanes which has 8 data lanes and 4 clock lanes.
44 * +---------+---------+---------+---------+--------+---------+----------+
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/linux-6.14.4/drivers/gpu/drm/sun4i/
Dsun6i_mipi_dsi.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2017-2018 Bootlin
11 #include <linux/crc-ccitt.h>
14 #include <linux/phy/phy-mipi-dphy.h>
293 regmap_update_bits(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG, in sun6i_dsi_inst_abort()
299 regmap_update_bits(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG, in sun6i_dsi_inst_commit()
308 return regmap_read_poll_timeout(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG, in sun6i_dsi_inst_wait_for_completion()
321 regmap_write(dsi->regs, SUN6I_DSI_INST_FUNC_REG(id), in sun6i_dsi_inst_setup()
332 u8 lanes_mask = GENMASK(device->lanes - 1, 0); in sun6i_dsi_inst_init()
359 regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_CFG_REG(0), in sun6i_dsi_inst_init()
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/linux-6.14.4/drivers/gpu/drm/rockchip/
Ddw-mipi-dsi2-rockchip.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Guochun Huang <hero.huang@rock-chips.com>
12 #include <linux/media-bus-format.h>
88 const struct dsigrf_reg *field = &dsi2->cdata->grf_regs[index]; in grf_field_write()
93 regmap_write(dsi2->grf_regmap, field->offset, in grf_field_write()
94 (val << field->lsb) | (GENMASK(field->msb, field->lsb) << 16)); in grf_field_write()
107 ret = phy_set_mode(dsi2->phy, PHY_MODE_MIPI_DPHY); in dw_mipi_dsi2_phy_power_on()
109 dev_err(dsi2->dev, "Failed to set phy mode: %d\n", ret); in dw_mipi_dsi2_phy_power_on()
113 phy_configure(dsi2->phy, &dsi2->phy_opts); in dw_mipi_dsi2_phy_power_on()
114 phy_power_on(dsi2->phy); in dw_mipi_dsi2_phy_power_on()
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/linux-6.14.4/drivers/pmdomain/starfive/
Djh71xx-pmu.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
15 #include <dt-bindings/power/starfive,jh7110-pmu.h>
29 /* sw encourage cfg */
87 struct jh71xx_pmu *pmu = pmd->pmu; in jh71xx_pmu_get_state()
90 return -EINVAL; in jh71xx_pmu_get_state()
92 *is_on = readl(pmu->base + pmu->match_data->pmu_status) & mask; in jh71xx_pmu_get_state()
99 struct jh71xx_pmu *pmu = pmd->pmu; in jh7110_pmu_set_state()
107 spin_lock_irqsave(&pmu->lock, flags); in jh7110_pmu_set_state()
129 writel(mask, pmu->base + mode); in jh7110_pmu_set_state()
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/linux-6.14.4/arch/arm64/boot/dts/ti/
Dk3-j784s4-j742s2-main-common.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/mux/mux.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/phy/phy-ti.h>
12 #include "k3-serdes.h"
15 serdes_refclk: clock-serdes {
16 #clock-cells = <0>;
17 compatible = "fixed-clock";
29 compatible = "mmio-sram";
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Dk3-j721s2-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
12 serdes_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
21 compatible = "mmio-sram";
23 #address-cells = <1>;
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/linux-6.14.4/drivers/phy/allwinner/
Dphy-sun4i-usb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2014-2015 Hans de Goede <[email protected]>
10 * Modelled after: Samsung S5P/Exynos SoC series MIPI CSIS/DSIM DPHY driver
18 #include <linux/extcon-provider.h>
27 #include <linux/phy/phy-sun4i-usb.h>
115 const struct sun4i_usb_phy_cfg *cfg; member
145 container_of((phy), struct sun4i_usb_phy_data, phys[(phy)->index])
153 iscr = readl(data->base + REG_ISCR); in sun4i_usb_phy0_update_iscr()
156 writel(iscr, data->base + REG_ISCR); in sun4i_usb_phy0_update_iscr()
183 u32 temp, usbc_bit = BIT(phy->index * 2); in sun4i_usb_phy_write()
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