1 // SPDX-License-Identifier: GPL-2.0-only
3  * Copyright (C) 2013--2024 Intel Corporation
14 #include <media/v4l2-async.h>
17 #include "ipu6-bus.h"
18 #include "ipu6-isys.h"
19 #include "ipu6-isys-csi2.h"
20 #include "ipu6-platform-isys-csi2-reg.h"
38  *  There are 2 MCD DPHY instances on TGL and 1 MCD DPHY instance on ADL.
39  *  Each MCD PHY has 12-lanes which has 8 data lanes and 4 clock lanes.
44  *  +---------+---------+---------+---------+--------+---------+----------+
47  *  +---------+---------+---------+---------+--------+---------+----------+
50  *  |---------+---------+---------+---------+--------+---------+----------+
53  *  ----------+---------+---------+---------+--------+---------+----------+
56  *  +---------+---------+---------+---------+--------+---------+----------+
59  *  +---------+---------+---------+---------+--------+---------+----------+
62  *  +---------+---------+---------+---------+--------+---------+----------+
65  *  +---------+---------+---------+---------+--------+---------+----------+
68  *  +---------+---------+---------+---------+--------+---------+----------+
71  *  |---------+---------+---------+---------+--------+---------+----------+
74  *  ----------+---------+---------+---------+--------+---------+----------+
77  *  +---------+---------+---------+---------+--------+---------+----------+
80  *  +---------+---------+---------+---------+--------+---------+----------+
83  *  +---------+---------+---------+---------+--------+---------+----------+
88  * Left : port0 - PPI range {0, 1, 2, 3, 4}
89  * Right: port2 - PPI range {6, 7, 8, 9, 10}
92  * Left: port0 - PPI range {0, 1, 2, 3, 4}
93  * Right: port2 - PPI range {6, 7, 8}, port3 - PPI range {9, 10, 11}
96  * Left: port0 - PPI range {0, 1, 2}, port1 - PPI range {3, 4, 5}
97  * Right: port2 - PPI range {6, 7, 8, 9, 10}
100  * Left : port0 - PPI range {0, 1, 2}, port1 - PPI range {3, 4, 5}
101  * Right: port2 - PPI range {6, 7, 8}, port3 - PPI range {9, 10, 11}
110 	/* for TGL-U, use 0x80000000 */
505 	struct device *dev = &isys->adev->auxdev.dev;  in ipu6_isys_mcd_phy_powerup_ack()
506 	void __iomem *isys_base = isys->pdata->base;  in ipu6_isys_mcd_phy_powerup_ack()
525 	struct device *dev = &isys->adev->auxdev.dev;  in ipu6_isys_mcd_phy_powerdown_ack()
526 	void __iomem *isys_base = isys->pdata->base;  in ipu6_isys_mcd_phy_powerdown_ack()
542 	void __iomem *isys_base = isys->pdata->base;  in ipu6_isys_mcd_phy_reset()
556 	struct device *dev = &isys->adev->auxdev.dev;  in ipu6_isys_mcd_phy_ready()
557 	void __iomem *isys_base = isys->pdata->base;  in ipu6_isys_mcd_phy_ready()
572 	struct ipu6_bus_device *adev = isys->adev;  in ipu6_isys_mcd_phy_common_init()
573 	struct ipu6_device *isp = adev->isp;  in ipu6_isys_mcd_phy_common_init()
574 	void __iomem *isp_base = isp->base;  in ipu6_isys_mcd_phy_common_init()
581 	list_for_each_entry(asc, &isys->notifier.done_list, asc_entry) {  in ipu6_isys_mcd_phy_common_init()
583 		phy_id = s_asd->csi2.port / 4;  in ipu6_isys_mcd_phy_common_init()
592 static int ipu6_isys_driver_port_to_phy_port(struct ipu6_isys_csi2_config *cfg)  in ipu6_isys_driver_port_to_phy_port()  argument
597 	if (!(cfg->nlanes == 4 || cfg->nlanes == 2 || cfg->nlanes == 1))  in ipu6_isys_driver_port_to_phy_port()
598 		return -EINVAL;  in ipu6_isys_driver_port_to_phy_port()
600 	/* B,F -> C0 A,E -> C1 C,G -> C2 D,H -> C4 */  in ipu6_isys_driver_port_to_phy_port()
602 	phy_port = cfg->port % 4;  in ipu6_isys_driver_port_to_phy_port()
613 	if (cfg->nlanes == 4 && !(phy_port == 0 || phy_port == 2))  in ipu6_isys_driver_port_to_phy_port()
614 		ret = -EINVAL;  in ipu6_isys_driver_port_to_phy_port()
615 	else if ((cfg->nlanes == 2 || cfg->nlanes == 1) &&  in ipu6_isys_driver_port_to_phy_port()
617 		ret = -EINVAL;  in ipu6_isys_driver_port_to_phy_port()
624 	struct device *dev = &isys->adev->auxdev.dev;  in ipu6_isys_mcd_phy_config()
625 	struct ipu6_bus_device *adev = isys->adev;  in ipu6_isys_mcd_phy_config()
627 	struct ipu6_device *isp = adev->isp;  in ipu6_isys_mcd_phy_config()
628 	void __iomem *isp_base = isp->base;  in ipu6_isys_mcd_phy_config()
630 	struct ipu6_isys_csi2_config cfg;  in ipu6_isys_mcd_phy_config()  local
636 	list_for_each_entry(asc, &isys->notifier.done_list, asc_entry) {  in ipu6_isys_mcd_phy_config()
638 		cfg.port = s_asd->csi2.port;  in ipu6_isys_mcd_phy_config()
639 		cfg.nlanes = s_asd->csi2.nlanes;  in ipu6_isys_mcd_phy_config()
640 		phy_port = ipu6_isys_driver_port_to_phy_port(&cfg);  in ipu6_isys_mcd_phy_config()
642 			dev_err(dev, "invalid port %d for lane %d", cfg.port,  in ipu6_isys_mcd_phy_config()
643 				cfg.nlanes);  in ipu6_isys_mcd_phy_config()
644 			return -ENXIO;  in ipu6_isys_mcd_phy_config()
647 		phy_id = cfg.port / 4;  in ipu6_isys_mcd_phy_config()
649 		dev_dbg(dev, "port%d PHY%u lanes %u\n", cfg.port, phy_id,  in ipu6_isys_mcd_phy_config()
650 			cfg.nlanes);  in ipu6_isys_mcd_phy_config()
652 		phy_config_regs = config_regs[cfg.nlanes / 2];  in ipu6_isys_mcd_phy_config()
653 		cfg.port = phy_port;  in ipu6_isys_mcd_phy_config()
654 		for (i = 0; phy_config_regs[cfg.port][i].reg; i++)  in ipu6_isys_mcd_phy_config()
655 			writel(phy_config_regs[cfg.port][i].val,  in ipu6_isys_mcd_phy_config()
656 			       phy_base + phy_config_regs[cfg.port][i].reg);  in ipu6_isys_mcd_phy_config()
666 				struct ipu6_isys_csi2_config *cfg,  in ipu6_isys_mcd_phy_set_power()  argument
670 	struct device *dev = &isys->adev->auxdev.dev;  in ipu6_isys_mcd_phy_set_power()
671 	void __iomem *isys_base = isys->pdata->base;  in ipu6_isys_mcd_phy_set_power()
676 	port = cfg->port;  in ipu6_isys_mcd_phy_set_power()
682 		cfg->nlanes);  in ipu6_isys_mcd_phy_set_power()
684 	if (!isys_base || port >= isys->pdata->ipdata->csi2.nports) {  in ipu6_isys_mcd_phy_set_power()
686 		return -EINVAL;  in ipu6_isys_mcd_phy_set_power()