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/linux-6.14.4/Documentation/sound/cards/
Dhdspm.rst2 Software Interface ALSA-DSP MADI Driver
5 (translated from German, so no good English ;-),
7 2004 - winfried ritsch
11 the Controls and startup-options are ALSA-Standard and only the
19 ------------------
21 * number of channels -- depends on transmission mode
29 * Single Speed -- 1..64 channels
37 * Double Speed -- 1..32 channels
40 Note: Choosing the 56-channel mode for
41 transmission/receive-mode , only 28 are transmitted/received
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/linux-6.14.4/sound/pci/echoaudio/
Dechoaudio.h3 Copyright Echo Digital Audio Corporation (c) 1998 - 2004
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston,
22 MA 02111-1307, USA.
26 Translation from C++ and adaptation for use in ALSA-Driver
34 +-----------+
35 record | |<-------------------- Inputs
36 <-------| | |
39 ------->| | +-------+
40 play | |--->|monitor|-------> Outputs
41 +-----------+ | mixer |
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Dechoaudio_dsp.h3 Copyright Echo Digital Audio Corporation (c) 1998 - 2004
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston,
22 MA 02111-1307, USA.
26 Translation from C++ and adaptation for use in ALSA-Driver
41 /**** Echo24: Gina24, Layla24, Mona, Mia, Mia-midi ****/
81 * These are the offsets for the memory-mapped DSP registers; the DSP base
133 #define MIDI_IN_SKIP_DATA (-1)
136 /*----------------------------------------------------------------------------
147 50 to 100 kHz inclusive for double speed mode.
151 -Set the clock select bits in the control register to 0xe (see the #define
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Dmona_dsp.c3 Copyright Echo Digital Audio Corporation (c) 1998 - 2004
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston,
22 MA 02111-1307, USA.
26 Translation from C++ and adaptation for use in ALSA-Driver
33 static int set_input_clock(struct echoaudio *chip, u16 clock);
45 return -ENODEV; in init_hw()
49 dev_err(chip->card->dev, in init_hw()
50 "init_hw - could not initialize DSP comm page\n"); in init_hw()
54 chip->device_id = device_id; in init_hw()
55 chip->subdevice_id = subdevice_id; in init_hw()
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/linux-6.14.4/drivers/ata/
Dpata_ftide010.c1 // SPDX-License-Identifier: GPL-2.0-only
24 * struct ftide010 - state container for the Faraday FTIDE010
27 * @pclk: peripheral clock for the IDE block
48 /* Gemini-specific properties */
93 * The unit of the below required timings is two clock periods of the ATA
94 * reference clock which is 30 nanoseconds per unit at 66MHz and 20
95 * nanoseconds per unit at 50 MHz. The PIO timings assume 33MHz speed for
142 struct ftide010 *ftide = ap->host->private_data; in ftide010_set_dmamode()
143 u8 speed = adev->dma_mode; in ftide010_set_dmamode() local
144 u8 devno = adev->devno & 1; in ftide010_set_dmamode()
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Dpata_opti.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_opti.c - ATI PATA for new ATA layer
9 * Copyright (C) 1996-1998 Linus Torvalds & authors (see below)
47 * opti_pre_reset - probe begin
56 struct ata_port *ap = link->ap; in opti_pre_reset()
57 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in opti_pre_reset()
63 if (!pci_test_config_bits(pdev, &opti_enable_bits[ap->port_no])) in opti_pre_reset()
64 return -ENOENT; in opti_pre_reset()
70 * opti_write_reg - control register setup
76 * rather than using PCI space as other controllers do. The double inw
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/linux-6.14.4/sound/soc/codecs/
Des7241.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
39 gpiod_set_value_cansleep(priv->reset, 0); in es7241_set_mode()
42 gpiod_set_value_cansleep(priv->m0, m0); in es7241_set_mode()
43 gpiod_set_value_cansleep(priv->m1, m1); in es7241_set_mode()
45 /* take the device out of reset - datasheet does not specify a delay */ in es7241_set_mode()
46 gpiod_set_value_cansleep(priv->reset, 1); in es7241_set_mode()
58 for (j = 0; j < mode->slv_mfs_num; j++) { in es7241_set_consumer_mode()
59 if (mode->slv_mfs[j] == mfs) in es7241_set_consumer_mode()
63 return -EINVAL; in es7241_set_consumer_mode()
75 * We can't really set clock ratio, if the mclk/lrclk is different in es7241_set_provider_mode()
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/linux-6.14.4/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
Dfsl,cpm1-tsa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC CPM Time-slot assigner (TSA) controller
10 - Herve Codina <[email protected]>
13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14 Its purpose is to route some TDM time-slots to other internal serial
20 - enum:
21 - fsl,mpc885-tsa
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Dfsl,qe-tsa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC QE Time-slot assigner (TSA) controller
10 - Herve Codina <[email protected]>
13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14 Its purpose is to route some TDM time-slots to other internal serial
20 - enum:
21 - fsl,mpc8321-tsa
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/linux-6.14.4/tools/spi/
Dspidev_test.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Cross-compile with cross-gcc -I/path/to/cross-kernel/include
43 static uint32_t speed = 500000; variable
72 while (length-- > 0) { in hex_dump()
92 * Unescape - process hexadecimal escape character
93 * converts shell input "\x23" -> 0x23
129 .speed_hz = speed, in transfer()
177 printf("Usage: %s [-2348CDFHILMNORSZbdilopsvw]\n", prog); in print_usage()
179 " -D --device device to use (default /dev/spidev1.1)\n" in print_usage()
180 " -s --speed max speed (Hz)\n" in print_usage()
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/linux-6.14.4/Documentation/devicetree/bindings/mmc/
Dmmc-controller-common.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-controller-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <[email protected]>
14 possible slots or ports for multi-slot controllers.
17 "#address-cells":
22 "#size-cells":
29 broken-cd:
34 cd-gpios:
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/linux-6.14.4/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/
Ddml2_dpmm_dcn4.c1 // SPDX-License-Identifier: MIT
10 static double dram_bw_kbps_to_uclk_khz(unsigned long long bandwidth_kbps, const struct dml2_dram_pa… in dram_bw_kbps_to_uclk_khz()
12 double uclk_khz = 0; in dram_bw_kbps_to_uclk_khz()
15 …uclk_mbytes_per_tick = dram_config->channel_count * dram_config->channel_width_bytes * dram_config… in dram_bw_kbps_to_uclk_khz()
17 uclk_khz = (double)bandwidth_kbps / uclk_mbytes_per_tick; in dram_bw_kbps_to_uclk_khz()
23 double *uclk, in get_minimum_clocks_for_latency()
24 double *fclk, in get_minimum_clocks_for_latency()
25 double *dcfclk) in get_minimum_clocks_for_latency()
29 if (in_out->display_cfg->stage3.success) in get_minimum_clocks_for_latency()
30 min_clock_index_for_latency = in_out->display_cfg->stage3.min_clk_index_for_latency; in get_minimum_clocks_for_latency()
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/linux-6.14.4/arch/powerpc/include/asm/
Duninorth.h1 /* SPDX-License-Identifier: GPL-2.0 */
14 * Uni-N and U3 config space reg. definitions
58 * This word contains, in little-endian format (!!!), the physical address
78 * Turning on AGP seem to require a double invalidate operation, one before
92 * Uni-N memory mapped reg. definitions
94 * Those registers are Big-Endian !!
114 #define UNI_N_CLOCK_CNTL_PCI 0x00000001 /* PCI2 clock control */
115 #define UNI_N_CLOCK_CNTL_GMAC 0x00000002 /* GMAC clock control */
116 #define UNI_N_CLOCK_CNTL_FW 0x00000004 /* FireWire clock control */
117 #define UNI_N_CLOCK_CNTL_ATA100 0x00000010 /* ATA-100 clock control (U2) */
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/linux-6.14.4/Documentation/arch/powerpc/
Ddawr-power9.rst18 clock : 3800.000000MHz
62 speed since it can use the hardware emulation. Unfortunately if this
97 To double check the DAWR is working, run this kernel selftest:
99 tools/testing/selftests/powerpc/ptrace/ptrace-hwbreak.c
/linux-6.14.4/drivers/usb/renesas_usbhs/
Dcommon.h1 /* SPDX-License-Identifier: GPL-1.0+ */
100 #define D2FIFOSEL 0x00F0 /* for R-Car Gen2 */
101 #define D2FIFOCTR 0x00F2 /* for R-Car Gen2 */
102 #define D3FIFOSEL 0x00F4 /* for R-Car Gen2 */
103 #define D3FIFOCTR 0x00F6 /* for R-Car Gen2 */
107 #define SCKE (1 << 10) /* USB Module Clock Enable */
108 #define CNEN (1 << 8) /* Single-ended receiver operation Enable */
109 #define HSE (1 << 7) /* High-Speed Operation Enable */
111 #define DRPD (1 << 5) /* D+ Line/D- Line Resistance Control */
114 #define UCKSEL (1 << 2) /* Clock Select for RZ/A1 */
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/linux-6.14.4/drivers/usb/dwc2/
Dcore.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
3 * core.h - DesignWare HS OTG Controller common declarations
5 * Copyright (C) 2004-2013 Synopsys, Inc.
21 * - no_printk: Disable tracing
22 * - pr_info: Print this info to the console
23 * - trace_printk: Print this info to trace buffer (good for verbose logging)
32 dev_name(hsotg->dev), ##__VA_ARGS__)
37 dev_name(hsotg->dev), ##__VA_ARGS__)
42 /* dwc2-hsotg declarations */
74 * struct dwc2_hsotg_ep - driver endpoint definition.
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/linux-6.14.4/Documentation/driver-api/i3c/
Dprotocol.rst1 .. SPDX-License-Identifier: GPL-2.0
17 https://resources.mipi.org/mipi-i3c-v1-download).
22 The I3C (pronounced 'eye-three-see') is a MIPI standardized protocol designed
23 to overcome I2C limitations (limited speed, external signals needed for
25 while remaining power-efficient.
42 I3C is a multi-master protocol, so there might be several masters on a bus,
51 In addition to these per-device addresses, the protocol defines a broadcast
70 * BCR: Bus Characteristic Register. This 8-bit register describes the device bus
72 * DCR: Device Characteristic Register. This 8-bit register describes the
74 * Provisioned ID: A 48-bit unique identifier. On a given bus there should be no
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/linux-6.14.4/drivers/net/wan/
Dfarsync.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Actually sync driver for X.21, V.35 and V.24 on FarSync T-series cards
23 * used with the FarSite T-Series cards (T2P & T4P) running in the high
24 * speed frame shifter mode. This is sometimes referred to as X.21 mode
30 * purpose (FarSite T-series).
104 unsigned char internalClock; /* 1 => internal clock, 0 => external */
105 unsigned int lineSpeed; /* Speed in bps */
113 unsigned char invertClock; /* Invert clock feature for syncing */
117 unsigned char structure; /* unframed, double, crc4, f4, f12, */
121 unsigned char lineBuildOut; /* 0, -7.5, -15, -22 */
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/linux-6.14.4/Documentation/networking/dsa/
Dbcm_sf2.rst8 - xDSL gateways such as BCM63138
9 - streaming/multimedia Set Top Box such as BCM7445
10 - Cable Modem/residential gateways such as BCM7145/BCM3390
13 ports, offering a range of built-in and customizable interfaces:
15 - single integrated Gigabit PHY
16 - quad integrated Gigabit PHY
17 - quad external Gigabit PHY w/ MDIO multiplexer
18 - integrated MoCA PHY
19 - several external MII/RevMII/GMII/RGMII interfaces
22 fail-over not to lose packets during a MoCA role re-election, as well as out of
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/linux-6.14.4/drivers/net/ethernet/freescale/fman/
Dfman.h1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later */
3 * Copyright 2008 - 2015 Freescale Semiconductor Inc.
21 /* TX-Port: Unsupported Format */
29 /* IPR non-consistent-sp */
66 /* non Frame-Manager error */
101 FMAN_EX_FPM_DOUBLE_ECC, /* Double ECC error on FPM ram access */
103 FMAN_EX_QMI_DOUBLE_ECC, /* Double bit ECC occurred on QMI */
109 FMAN_EX_IRAM_ECC, /* Double bit ECC occurred on IRAM */
110 FMAN_EX_MURAM_ECC /* Double bit ECC occurred on MURAM */
122 __be16 cksum; /* Running-sum */
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/linux-6.14.4/sound/pci/rme9652/
Dhdspm.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * Modified 2006-06-01 for AES32 support by Remy Bruno
12 * Modified 2009-04-13 for proper metering by Florian Faber
15 * Modified 2009-04-14 for native float support by Florian Faber
18 * Modified 2009-04-26 fixed bug in rms metering by Florian Faber
21 * Modified 2009-04-30 added hw serial number support by Florian Faber
23 * Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth
25 * Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth
27 * Modified 2019-05-23 fix AIO single speed ADAT capture and playback
35 * --------- HDSPM_controlRegister ---------
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/linux-6.14.4/include/linux/usb/
Dr8a66597.h1 // SPDX-License-Identifier: GPL-2.0
124 #define XTAL 0xC000 /* b15-14: Crystal selection */
128 #define XCKE 0x2000 /* b13: External clock enable */
130 #define SCKE 0x0400 /* b10: USB clock enable */
133 #define HSE 0x0080 /* b7: Hi-speed enable */
135 #define DRPD 0x0020 /* b5: D+/- pull down control */
140 #define OVCBIT 0x8000 /* b15-14: Over-current bit */
141 #define OVCMON 0xC000 /* b15-14: Over-current monitor */
143 #define IDMON 0x0004 /* b3: ID-pin monitor */
144 #define LNST 0x0003 /* b1-0: D+, D- line status */
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/linux-6.14.4/drivers/usb/gadget/udc/
Dpxa25x_udc.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Intel PXA25x and IXP4xx on-chip full speed USB device controllers
30 #include <linux/dma-mapping.h>
40 #include <asm/mach-types.h>
48 #define UDC_RES1 0x0004 /* UDC Undocumented - Reserved1 */
49 #define UDC_RES2 0x0008 /* UDC Undocumented - Reserved2 */
50 #define UDC_RES3 0x000C /* UDC Undocumented - Reserved3 */
211 * not used here. IN-DMA (to host) is simple enough, when the data is
213 * other software can. OUT-DMA is buggy in most chip versions, as well
215 * bother using DMA. (Mostly-working IN-DMA support was available in
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Dm66592-udc.h1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2006-2007 Renesas Solutions Corp.
17 #define M66592_XTAL 0xC000 /* b15-14: Crystal selection */
21 #define M66592_XCKE 0x2000 /* b13: External clock enable */
22 #define M66592_RCKE 0x1000 /* b12: Register clock enable */
24 #define M66592_SCKE 0x0400 /* b10: USB clock enable */
25 #define M66592_ATCKM 0x0100 /* b8: Automatic clock supply */
26 #define M66592_HSE 0x0080 /* b7: Hi-speed enable */
28 #define M66592_DMRPD 0x0020 /* b5: D- pull down control */
30 #define M66592_FSRPC 0x0004 /* b2: Full-speed receiver enable */
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/linux-6.14.4/drivers/net/ethernet/freescale/
Dfec_ptp.c1 // SPDX-License-Identifier: GPL-2.0
93 * fec_ptp_read - read raw cycle counter (to be used by time counter)
106 tempval = readl(fep->hwp + FEC_ATIME_CTRL); in fec_ptp_read()
108 writel(tempval, fep->hwp + FEC_ATIME_CTRL); in fec_ptp_read()
110 if (fep->quirks & FEC_QUIRK_BUG_CAPTURE) in fec_ptp_read()
113 return readl(fep->hwp + FEC_ATIME); in fec_ptp_read()
130 spin_lock_irqsave(&fep->tmreg_lock, flags); in fec_ptp_enable_pps()
132 if (fep->pps_enable == enable) { in fec_ptp_enable_pps()
133 spin_unlock_irqrestore(&fep->tmreg_lock, flags); in fec_ptp_enable_pps()
140 writel(FEC_T_TF_MASK, fep->hwp + FEC_TCSR(fep->pps_channel)); in fec_ptp_enable_pps()
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