Lines Matching +full:double +full:- +full:speed +full:- +full:clock
3 Copyright Echo Digital Audio Corporation (c) 1998 - 2004
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston,
22 MA 02111-1307, USA.
26 Translation from C++ and adaptation for use in ALSA-Driver
33 static int set_input_clock(struct echoaudio *chip, u16 clock);
45 return -ENODEV; in init_hw()
49 dev_err(chip->card->dev, in init_hw()
50 "init_hw - could not initialize DSP comm page\n"); in init_hw()
54 chip->device_id = device_id; in init_hw()
55 chip->subdevice_id = subdevice_id; in init_hw()
56 chip->bad_board = true; in init_hw()
57 chip->input_clock_types = in init_hw()
60 chip->digital_modes = in init_hw()
66 if (chip->device_id == DEVICE_ID_56361) in init_hw()
67 chip->dsp_code_to_load = FW_MONA_361_DSP; in init_hw()
69 chip->dsp_code_to_load = FW_MONA_301_DSP; in init_hw()
74 chip->bad_board = false; in init_hw()
83 chip->digital_mode = DIGITAL_MODE_SPDIF_RCA; in set_mixer_defaults()
84 chip->professional_spdif = false; in set_mixer_defaults()
85 chip->digital_in_automute = true; in set_mixer_defaults()
95 /* Map the DSP clock detect bits to the generic driver clock in detect_input_clocks()
97 clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks); in detect_input_clocks()
123 if (chip->asic_loaded) in load_asic()
128 if (chip->device_id == DEVICE_ID_56361) in load_asic()
137 chip->asic_code = asic; in load_asic()
149 /* Set up the control register if the load succeeded - in load_asic()
150 48 kHz, internal clock, S/PDIF RCA mode */ in load_asic()
169 /* Check the clock detect bits to see if this is in switch_asic()
170 a single-speed clock or a double-speed clock; load in switch_asic()
172 if (chip->device_id == DEVICE_ID_56361) { in switch_asic()
184 if (asic != chip->asic_code) { in switch_asic()
190 chip->asic_code = asic; in switch_asic()
200 u32 control_reg, clock; in set_sample_rate() local
204 /* Only set the clock for internal mode. */ in set_sample_rate()
205 if (chip->input_clock != ECHO_CLOCK_INTERNAL) { in set_sample_rate()
206 dev_dbg(chip->card->dev, in set_sample_rate()
207 "Cannot set sample rate - clock not set to CLK_CLOCKININTERNAL\n"); in set_sample_rate()
209 chip->comm_page->sample_rate = cpu_to_le32(rate); in set_sample_rate()
210 chip->sample_rate = rate; in set_sample_rate()
216 if (chip->digital_mode == DIGITAL_MODE_ADAT) in set_sample_rate()
217 return -EINVAL; in set_sample_rate()
218 if (chip->device_id == DEVICE_ID_56361) in set_sample_rate()
223 if (chip->device_id == DEVICE_ID_56361) in set_sample_rate()
230 if (asic != chip->asic_code) { in set_sample_rate()
233 spin_unlock_irq(&chip->lock); in set_sample_rate()
236 spin_lock_irq(&chip->lock); in set_sample_rate()
240 chip->asic_code = asic; in set_sample_rate()
245 clock = 0; in set_sample_rate()
246 control_reg = le32_to_cpu(chip->comm_page->control_register); in set_sample_rate()
252 clock = GML_96KHZ; in set_sample_rate()
255 clock = GML_88KHZ; in set_sample_rate()
258 clock = GML_48KHZ | GML_SPDIF_SAMPLE_RATE1; in set_sample_rate()
261 clock = GML_44KHZ; in set_sample_rate()
264 clock |= GML_SPDIF_SAMPLE_RATE0; in set_sample_rate()
267 clock = GML_32KHZ | GML_SPDIF_SAMPLE_RATE0 | in set_sample_rate()
271 clock = GML_22KHZ; in set_sample_rate()
274 clock = GML_16KHZ; in set_sample_rate()
277 clock = GML_11KHZ; in set_sample_rate()
280 clock = GML_8KHZ; in set_sample_rate()
283 dev_err(chip->card->dev, in set_sample_rate()
285 return -EINVAL; in set_sample_rate()
288 control_reg |= clock; in set_sample_rate()
290 chip->comm_page->sample_rate = cpu_to_le32(rate); /* ignored by the DSP */ in set_sample_rate()
291 chip->sample_rate = rate; in set_sample_rate()
292 dev_dbg(chip->card->dev, in set_sample_rate()
293 "set_sample_rate: %d clock %d\n", rate, clock); in set_sample_rate()
300 static int set_input_clock(struct echoaudio *chip, u16 clock) in set_input_clock() argument
305 /* Mask off the clock select bits */ in set_input_clock()
306 control_reg = le32_to_cpu(chip->comm_page->control_register) & in set_input_clock()
308 clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks); in set_input_clock()
310 switch (clock) { in set_input_clock()
312 chip->input_clock = ECHO_CLOCK_INTERNAL; in set_input_clock()
313 return set_sample_rate(chip, chip->sample_rate); in set_input_clock()
315 if (chip->digital_mode == DIGITAL_MODE_ADAT) in set_input_clock()
316 return -EAGAIN; in set_input_clock()
317 spin_unlock_irq(&chip->lock); in set_input_clock()
320 spin_lock_irq(&chip->lock); in set_input_clock()
330 spin_unlock_irq(&chip->lock); in set_input_clock()
333 spin_lock_irq(&chip->lock); in set_input_clock()
343 dev_dbg(chip->card->dev, "Set Mona clock to ADAT\n"); in set_input_clock()
344 if (chip->digital_mode != DIGITAL_MODE_ADAT) in set_input_clock()
345 return -EAGAIN; in set_input_clock()
350 dev_err(chip->card->dev, in set_input_clock()
351 "Input clock 0x%x not supported for Mona\n", clock); in set_input_clock()
352 return -EINVAL; in set_input_clock()
355 chip->input_clock = clock; in set_input_clock()
366 /* Set clock to "internal" if it's not compatible with the new mode */ in dsp_set_digital_mode()
371 if (chip->input_clock == ECHO_CLOCK_ADAT) in dsp_set_digital_mode()
375 if (chip->input_clock == ECHO_CLOCK_SPDIF) in dsp_set_digital_mode()
379 dev_err(chip->card->dev, in dsp_set_digital_mode()
381 return -EINVAL; in dsp_set_digital_mode()
384 spin_lock_irq(&chip->lock); in dsp_set_digital_mode()
387 chip->sample_rate = 48000; in dsp_set_digital_mode()
392 control_reg = le32_to_cpu(chip->comm_page->control_register); in dsp_set_digital_mode()
406 if (chip->asic_code == FW_MONA_361_1_ASIC96 || in dsp_set_digital_mode()
407 chip->asic_code == FW_MONA_301_1_ASIC96) { in dsp_set_digital_mode()
416 spin_unlock_irq(&chip->lock); in dsp_set_digital_mode()
419 chip->digital_mode = mode; in dsp_set_digital_mode()
421 dev_dbg(chip->card->dev, "set_digital_mode to %d\n", mode); in dsp_set_digital_mode()