| /linux-6.14.4/Documentation/devicetree/bindings/dma/ |
| D | fsl,edma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/fsl,edma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The eDMA channels have multiplex capability by programmable
11 memory-mapped registers. channels are split into two groups, called
12 DMAMUX0 and DMAMUX1, specific DMA request source can only be multiplexed
16 - Peng Fan <[email protected]>
21 - enum:
22 - fsl,vf610-edma
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| D | owl-dma.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/dma/owl-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Actions Semi Owl SoCs DMA controller
10 The OWL DMA is a general-purpose direct memory access controller capable of
11 supporting 10 independent DMA channels for the Actions Semi S700 SoC and 12
12 independent DMA channels for the S500 and S900 SoC variants.
15 - Manivannan Sadhasivam <[email protected]>
18 - $ref: dma-controller.yaml#
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| D | brcm,bcm2835-dma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/brcm,bcm2835-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: BCM2835 DMA controller
10 - Nicolas Saenz Julienne <[email protected]>
13 The BCM2835 DMA controller has 16 channels in total. Only the lower
14 13 channels have an associated IRQ. Some arbitrary channels are used by the
15 VideoCore firmware (1,3,6,7 in the current firmware version). The channels
19 - $ref: dma-controller.yaml#
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| D | ingenic,dma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/ingenic,dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ingenic SoCs DMA Controller
10 - Paul Cercueil <[email protected]>
13 - $ref: dma-controller.yaml#
18 - enum:
19 - ingenic,jz4740-dma
20 - ingenic,jz4725b-dma
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| D | dma-common.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/dma/dma-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DMA Engine Common Properties
10 - Vinod Koul <[email protected]>
13 Generic binding to provide a way for a driver using DMA Engine to
14 retrieve the DMA request or channel information that goes from a
15 hardware device to a DMA controller.
20 "#dma-cells":
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| D | sprd,sc9860-dma.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/dma/sprd,sc9860-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Spreadtrum SC9860 DMA controller
10 There are three DMA controllers: AP DMA, AON DMA and AGCP DMA. For AGCP
11 DMA controller, it can or do not request the IRQ, which will save
12 system power without resuming system by DMA interrupts if AGCP DMA
16 - Orson Zhai <[email protected]>
17 - Baolin Wang <[email protected]>
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| D | snps,dma-spear1340.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/dma/snps,dma-spear1340.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys Designware DMA Controller
10 - Viresh Kumar <[email protected]>
11 - Andy Shevchenko <[email protected]>
14 - $ref: dma-controller.yaml#
19 - const: snps,dma-spear1340
20 - items:
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| D | apple,admac.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/dma/apple,admac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Apple Audio DMA Controller (ADMAC)
10 Apple's Audio DMA Controller (ADMAC) is used to fetch and store audio samples
13 The controller has been seen with up to 24 channels. Even-numbered channels
14 are TX-only, odd-numbered are RX-only. Individual channels are coupled to
18 - Martin Povišer <[email protected]>
21 - $ref: dma-controller.yaml#
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| D | ti-edma.txt | 4 Controller(s) (TC). The CC is the main entry for DMA users since it is
5 responsible for the DMA channel handling, while the TCs are responsible to
6 execute the actual DMA tansfer.
8 ------------------------------------------------------------------------------
12 --------------------
13 - compatible: Should be:
14 - "ti,edma3-tpcc" for the channel controller(s) on OMAP,
16 - "ti,k2g-edma3-tpcc", "ti,edma3-tpcc" for the
18 - #dma-cells: Should be set to <2>. The first number is the DMA request
20 - reg: Memory map of eDMA CC
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| D | snps,dw-axi-dmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/snps,dw-axi-dmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare AXI DMA Controller
10 - Eugeniy Paltsev <[email protected]>
13 Synopsys DesignWare AXI DMA Controller DT Binding
16 - $ref: dma-controller.yaml#
21 - snps,axi-dma-1.01a
22 - intel,kmb-axi-dma
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| D | st_fdma.txt | 3 The FDMA is a general-purpose direct memory access controller capable of
4 supporting 16 independent DMA channels. It accepts up to 32 DMA requests.
10 - compatible : Should be one of
11 - st,stih407-fdma-mpe31-11, "st,slim-rproc";
12 - st,stih407-fdma-mpe31-12, "st,slim-rproc";
13 - st,stih407-fdma-mpe31-13, "st,slim-rproc";
14 - reg : Should contain an entry for each name in reg-names
15 - reg-names : Must contain "slimcore", "dmem", "peripherals", "imem" entries
16 - interrupts : Should contain one interrupt shared by all channels
17 - dma-channels : Number of channels supported by the controller
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| D | k3dma.txt | 1 * Hisilicon K3 DMA controller
3 See dma.txt first
6 - compatible: Must be one of
7 - "hisilicon,k3-dma-1.0"
8 - "hisilicon,hisi-pcm-asp-dma-1.0"
9 - reg: Should contain DMA registers location and length.
10 - interrupts: Should contain one interrupt shared by all channel
11 - #dma-cells: see dma.txt, should be 1, para number
12 - dma-channels: physical channels supported
13 - dma-requests: virtual channels supported, each virtual channel
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| D | fsl,mxs-dma.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/dma/fsl,mxs-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Direct Memory Access (DMA) Controller from i.MX23/i.MX28
10 - Marek Vasut <[email protected]>
13 - $ref: dma-controller.yaml#
14 - if:
18 const: fsl,imx8qxp-dma-apbh
21 - power-domains
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| D | socionext,uniphier-xdmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/socionext,uniphier-xdmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier external DMA controller
10 This describes the devicetree bindings for an external DMA engine to perform
11 memory-to-memory or peripheral-to-memory data transfer capable of supporting
12 16 channels, implemented in Socionext UniPhier SoCs.
15 - Kunihiko Hayashi <[email protected]>
18 - $ref: dma-controller.yaml#
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| /linux-6.14.4/drivers/iio/adc/ |
| D | ti_am335x_adc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
26 #include <linux/dma-mapping.h>
43 struct tiadc_dma dma; member
45 int channels; member
56 return readl(adc->mfd_tscadc->tscadc_base + reg); in tiadc_readl()
62 writel(val, adc->mfd_tscadc->tscadc_base + reg); in tiadc_writel()
69 step_en = ((1 << adc_dev->channels) - 1); in get_adc_step_mask()
70 step_en <<= TOTAL_STEPS - adc_dev->channels + 1; in get_adc_step_mask()
79 for (i = 0; i < ARRAY_SIZE(adc_dev->channel_step); i++) { in get_adc_chan_step_mask()
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| /linux-6.14.4/Documentation/devicetree/bindings/dma/xilinx/ |
| D | xilinx_dma.txt | 2 It can be configured to have one channel or two channels. If configured
3 as two channels, one is to transmit to the video device and another is
6 Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream
7 target devices. It can be configured to have one channel or two channels.
8 If configured as two channels, one is to transmit to the device and another
11 Xilinx AXI CDMA engine, it does transfers between memory-mapped source
12 address and a memory-mapped destination address.
16 and receive channels.
19 - compatible: Should be one of-
20 "xlnx,axi-vdma-1.00.a"
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| /linux-6.14.4/arch/mips/include/asm/ |
| D | dma.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * linux/include/asm/dma.h: Defines for using and allocating dma channels.
5 * High DMA channel support & info by Hannu Savolainen
9 * and can only be used for expansion cards. Onboard DMA controllers, such
30 * NOTES about DMA transfers:
32 * controller 1: channels 0-3, byte operations, ports 00-1F
33 * controller 2: channels 4-7, word operations, ports C0-DF
35 * - ALL registers are 8 bits only, regardless of transfer size
36 * - channel 4 is not used - cascades 1 into 2.
37 * - channels 0-3 are byte - addresses/counts are for physical bytes
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| /linux-6.14.4/arch/x86/include/asm/ |
| D | dma.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * linux/include/asm/dma.h: Defines for using and allocating dma channels.
5 * High DMA channel support & info by Hannu Savolainen
24 * NOTES about DMA transfers:
26 * controller 1: channels 0-3, byte operations, ports 00-1F
27 * controller 2: channels 4-7, word operations, ports C0-DF
29 * - ALL registers are 8 bits only, regardless of transfer size
30 * - channel 4 is not used - cascades 1 into 2.
31 * - channels 0-3 are byte - addresses/counts are for physical bytes
32 * - channels 5-7 are word - addresses/counts are for physical words
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| /linux-6.14.4/arch/alpha/include/asm/ |
| D | dma.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * include/asm-alpha/dma.h
5 * This is essentially the same as the i386 DMA stuff, as the AlphaPCs
6 * use ISA-compatible dma. The only extension is support for high-page
7 * registers that allow to set the top 8 bits of a 32-bit DMA address.
8 * This register should be written last when setting up a DMA address
9 * as this will also enable DMA across 64 KB boundaries.
12 /* $Id: dma.h,v 1.7 1992/12/14 00:29:34 root Exp root $
13 * linux/include/asm/dma.h: Defines for using and allocating dma channels.
15 * High DMA channel support & info by Hannu Savolainen
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| /linux-6.14.4/arch/powerpc/include/asm/ |
| D | dma.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
7 * Defines for using and allocating dma channels.
9 * High DMA channel support & info by Hannu Savolainen
19 * basically just enough here to get kernel/dma.c to compile.
29 /* The maximum address that we can perform a DMA transfer to on this platform */
42 * NOTES about DMA transfers:
44 * controller 1: channels 0-3, byte operations, ports 00-1F
45 * controller 2: channels 4-7, word operations, ports C0-DF
47 * - ALL registers are 8 bits only, regardless of transfer size
48 * - channel 4 is not used - cascades 1 into 2.
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| /linux-6.14.4/include/linux/ |
| D | timb_dma.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * timb_dma.h timberdale FPGA DMA driver defines
8 * Timberdale FPGA DMA engine
15 * struct timb_dma_platform_data_channel - Description of each individual
16 * DMA channel for the timberdale DMA driver
19 * @bytes_per_line: Number of bytes per line, this is specific for channels
20 * handling video data. For other channels this shall be left to 0.
33 * struct timb_dma_platform_data - Platform data of the timberdale DMA driver
34 * @nr_channels: Number of defined channels in the channels array.
35 * @channels: Definition of the each channel.
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| /linux-6.14.4/Documentation/devicetree/bindings/usb/ |
| D | da8xx-usb.txt | 3 For DA8xx/OMAP-L1x/AM17xx/AM18xx platforms.
7 - compatible : Should be set to "ti,da830-musb".
9 - reg: Offset and length of the USB controller register set.
11 - interrupts: The USB interrupt number.
13 - interrupt-names: Should be set to "mc".
15 - dr_mode: The USB operation mode. Should be one of "host", "peripheral" or "otg".
17 - phys: Phandle for the PHY device
19 - phy-names: Should be "usb-phy"
21 - dmas: specifies the dma channels
23 - dma-names: specifies the names of the channels. Use "rxN" for receive
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| /linux-6.14.4/Documentation/driver-api/dmaengine/ |
| D | dmatest.rst | 2 DMA Test Guide
7 This small document introduces how to test DMA drivers using dmatest module.
9 The dmatest module tests DMA memcpy, memset, XOR and RAID6 P+Q operations using
11 will initialize both buffers with a repeatable pattern and verify that the DMA
16 test multiple channels at the same time, and it can start multiple threads
20 The test suite works only on the channels that have at least one
21 capability of the following: DMA_MEMCPY (memory-to-memory), DMA_MEMSET
22 (const-to-memory or memory-to-memory, when emulated), DMA_XOR, DMA_PQ.
28 Part 1 - How to build the test module
33 Device Drivers -> DMA Engine support -> DMA Test client
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| /linux-6.14.4/Documentation/devicetree/bindings/dma/ti/ |
| D | k3-udma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
5 ---
6 $id: http://devicetree.org/schemas/dma/ti/k3-udma.yaml#
7 $schema: http://devicetree.org/meta-schemas/core.yaml#
9 title: Texas Instruments K3 NAVSS Unified DMA
12 - Peter Ujfalusi <[email protected]>
15 The UDMA-P is intended to perform similar (but significantly upgraded)
16 functions as the packet-oriented DMA used on previous SoC devices. The UDMA-P
18 The UDMA-P architecture facilitates the segmentation and reassembly of SoC DMA
21 Multiple Tx and Rx channels are provided within the DMA which allow multiple
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| /linux-6.14.4/Documentation/devicetree/bindings/powerpc/fsl/ |
| D | dma.txt | 1 * Freescale DMA Controllers
3 ** Freescale Elo DMA Controller
4 This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
9 - compatible : must include "fsl,elo-dma"
10 - reg : DMA General Status Register, i.e. DGSR which contains
11 status for all the 4 DMA channels
12 - ranges : describes the mapping between the address space of the
13 DMA channels and the address space of the DMA controller
14 - cell-index : controller index. 0 for controller @ 0x8100
15 - interrupts : interrupt specifier for DMA IRQ
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