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/linux-6.14.4/drivers/mmc/host/
Ddw_mmc-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <linux/mmc/slot-gpio.h>
16 #include "dw_mmc-pltfm.h"
41 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
44 static int rockchip_mmc_get_internal_phase(struct dw_mci *host, bool sample) in rockchip_mmc_get_internal_phase() argument
46 unsigned long rate = clk_get_rate(host->ciu_clk); in rockchip_mmc_get_internal_phase()
51 /* Constant signal, no measurable phase shift */ in rockchip_mmc_get_internal_phase()
55 if (sample) in rockchip_mmc_get_internal_phase()
76 static int rockchip_mmc_get_phase(struct dw_mci *host, bool sample) in rockchip_mmc_get_phase() argument
78 struct dw_mci_rockchip_priv_data *priv = host->priv; in rockchip_mmc_get_phase()
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Ddw_mmc-starfive.c1 // SPDX-License-Identifier: GPL-2.0
19 #include "dw_mmc-pltfm.h"
31 if (ios->timing == MMC_TIMING_MMC_DDR52 || ios->timing == MMC_TIMING_UHS_DDR50) { in dw_mci_starfive_set_ios()
32 clock = (ios->clock > 50000000 && ios->clock <= 52000000) ? 100000000 : ios->clock; in dw_mci_starfive_set_ios()
33 ret = clk_set_rate(host->ciu_clk, clock); in dw_mci_starfive_set_ios()
35 dev_dbg(host->dev, "Use an external frequency divider %uHz\n", ios->clock); in dw_mci_starfive_set_ios()
36 host->bus_hz = clk_get_rate(host->ciu_clk); in dw_mci_starfive_set_ios()
38 dev_dbg(host->dev, "Using the internal divider\n"); in dw_mci_starfive_set_ios()
44 /* change driver phase and sample phase */ in dw_mci_starfive_set_sample_phase()
60 struct dw_mci *host = slot->host; in dw_mci_starfive_execute_tuning()
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Dsdhci-of-arasan.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2011 - 2012 Michal Simek <[email protected]>
9 * Based on sdhci-of-esdhc.c
18 #include <linux/clk-provider.h>
26 #include <linux/firmware/xlnx-zynqmp.h>
29 #include "sdhci-cqhci.h"
30 #include "sdhci-pltfm.h"
81 /* Default settings for ZynqMP Clock Phases */
94 * On some SoCs the syscon area has a feature where the upper 16-bits of
95 * each 32-bit register act as a write mask for the lower 16-bits. This allows
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/linux-6.14.4/Documentation/devicetree/bindings/mmc/
Drockchip-dw-mshc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/rockchip-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
13 controller that are not already included in the synopsys-dw-mshc-common.yaml
17 - $ref: synopsys-dw-mshc-common.yaml#
20 - Heiko Stuebner <[email protected]>
27 - const: rockchip,rk2928-dw-mshc
29 - const: rockchip,rk3288-dw-mshc
30 - items:
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Dhisilicon,hi3798cv200-dw-mshc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mmc/hisilicon,hi3798cv200-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Yang Xiwen <[email protected]>
15 - hisilicon,hi3798cv200-dw-mshc
16 - hisilicon,hi3798mv200-dw-mshc
26 - description: bus interface unit clock
27 - description: card interface unit clock
28 - description: card input sample phase clock
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/linux-6.14.4/drivers/iio/resolver/
Dad2s1210.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2010-2010 Analog Devices Inc.
11 * ----------------------------|------|-------------------------------------------
20 * Phase lock range | D5 | events/in_phase0_mag_rising_value
23 * Resolution | D1:0 | *device tree: assigned-resolution-bits*
34 * ----------------------------------------|----|---------------------------------
41 * Phase error exceeds phase lock range | D1 | phase0 | mag | rising
142 /** GPIO pin connected to SAMPLE line. */
152 /* adi,fixed-mode property - only valid when mode_gpios == NULL. */
158 /** For reading raw sample value via SPI. */
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/linux-6.14.4/Documentation/networking/
Dcan.rst2 SocketCAN - Controller Area Network
20 .. _socketcan-motivation:
29 functionality. Usually, there is only a hardware-specific device
32 Queueing of frames and higher-level transport protocols like ISO-TP
34 character-device implementations support only one single process to
47 protocol family module and also vice-versa. Also, the protocol family
57 communicate using a specific transport protocol, e.g. ISO-TP, just
60 CAN-IDs, frames, etc.
62 Similar functionality visible from user-space could be provided by a
74 * **Abstraction:** In most existing character-device implementations, the
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/linux-6.14.4/drivers/clk/rockchip/
Dclk-mmc-phase.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
40 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
53 /* Constant signal, no measurable phase shift */ in rockchip_mmc_get_phase()
57 raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift); in rockchip_mmc_get_phase()
85 * MMC host to the card, which expects the phase clock inherits in rockchip_mmc_set_phase()
97 return -EINVAL; in rockchip_mmc_set_phase()
105 * actually go non-monotonic. We don't go _too_ monotonic in rockchip_mmc_set_phase()
124 * don't overflow 32-bit / 64-bit numbers. in rockchip_mmc_set_phase()
137 writel(HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock->shift), in rockchip_mmc_set_phase()
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/linux-6.14.4/Documentation/driver-api/media/drivers/
Dcx88-devel.rst1 .. SPDX-License-Identifier: GPL-2.0
9 -------------------------------------------
13 .. code-block:: none
15 Previous default from DScaler: 0x1c1f0008
16 Digit 8: 31-28
19 Digit 7: 27-24 (0xc = 12 = b1100 )
24 Digits 6,5: 23-16
25 25-16: COMB_RANGE = 0x1f [default] (9 bits -> max 512)
27 Digit 4: 15-12
33 Digit 3: 11-8
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/linux-6.14.4/arch/arm/boot/dts/rockchip/
Drv1126-sonoff-ihost.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
16 stdout-path = "serial2:1500000n8";
19 vcc5v0_sys: regulator-vcc5v0-sys {
20 compatible = "regulator-fixed";
21 regulator-name = "vcc5v0_sys";
22 regulator-always-on;
23 regulator-boot-on;
24 regulator-min-microvolt = <5000000>;
25 regulator-max-microvolt = <5000000>;
28 sdio_pwrseq: pwrseq-sdio {
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Drv1126-edgeble-neu2.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 compatible = "edgeble,neural-compute-module-2", "rockchip,rv1126";
14 vccio_flash: regulator-vccio-flash {
15 compatible = "regulator-fixed";
16 enable-active-high;
18 pinctrl-names = "default";
19 pinctrl-0 = <&flash_vol_sel>;
20 regulator-name = "vccio_flash";
21 regulator-always-on;
22 regulator-boot-on;
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Drv1126-edgeble-neu2-io.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include "rv1126-edgeble-neu2.dtsi"
13 compatible = "edgeble,neural-compute-module-2-io",
14 "edgeble,neural-compute-module-2", "rockchip,rv1126";
21 stdout-path = "serial2:1500000n8";
24 vcc12v_dcin: regulator-vcc12v-dcin {
25 compatible = "regulator-fixed";
26 regulator-name = "vcc12v_dcin";
27 regulator-always-on;
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Drk3288-veyron-sdmmc.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
15 sdcard-supply = <&vccio_sd>;
24 sdmmc_bus4: sdmmc-bus4 {
31 sdmmc_clk: sdmmc-clk {
35 sdmmc_cmd: sdmmc-cmd {
45 sdmmc_cd_disabled: sdmmc-cd-disabled {
50 sdmmc_cd_pin: sdmmc-cd-pin {
57 vcc9-supply = <&vcc_5v>;
61 regulator-name = "vccio_sd";
62 regulator-min-microvolt = <1800000>;
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/linux-6.14.4/sound/soc/meson/
Daxg-tdm-interface.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
11 #include <sound/soc-dai.h>
13 #include "axg-tdm.h"
53 dev_err(dai->dev, "interface has no slot\n"); in axg_tdm_set_tdm_slots()
54 return -EINVAL; in axg_tdm_set_tdm_slots()
57 iface->slots = slots; in axg_tdm_set_tdm_slots()
76 default: in axg_tdm_set_tdm_slots()
77 dev_err(dai->dev, "unsupported slot width: %d\n", slot_width); in axg_tdm_set_tdm_slots()
78 return -EINVAL; in axg_tdm_set_tdm_slots()
81 iface->slot_width = slot_width; in axg_tdm_set_tdm_slots()
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/linux-6.14.4/drivers/iio/dac/
Dadi-axi-dac.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright 2016-2024 Analog Devices Inc.
26 #include <linux/fpga/adi-axi-common.h>
28 #include <linux/iio/buffer-dmaengine.h>
32 #include "ad3552r-hs.h"
126 guard(mutex)(&st->lock); in axi_dac_enable()
127 ret = regmap_set_bits(st->regmap, AXI_DAC_RSTN_REG, in axi_dac_enable()
136 ret = regmap_read_poll_timeout(st->regmap, AXI_DAC_DRP_STATUS_REG, in axi_dac_enable()
143 return regmap_set_bits(st->regmap, AXI_DAC_RSTN_REG, in axi_dac_enable()
151 guard(mutex)(&st->lock); in axi_dac_disable()
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/linux-6.14.4/tools/testing/selftests/ptp/
Dtestptp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * PTP 1588 clock support - User space test program
35 #define CLOCK_INVALID -1
113 return t->sec * NSEC_PER_SEC + t->nsec; in pctns()
120 " -c query the ptp clock's capabilities\n" in usage()
121 " -d name device to open\n" in usage()
122 " -e val read 'val' external time stamp events\n" in usage()
123 " -f val adjust the ptp clock frequency by 'val' ppb\n" in usage()
124 " -F chan Enable single channel mask and keep device open for debugfs verification.\n" in usage()
125 " -g get the ptp clock time\n" in usage()
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/linux-6.14.4/Documentation/trace/rv/
Dda_monitor_instrumentation.rst51 --------------------------
84 Otherwise, the monitor and the system could be out-of-sync.
113 ----------------------------
132 But no change was required because: by default, these functions *attach* and
136 -----------------------
139 kernel event, at the monitoring enable phase.
143 adds "rv_attach_trace_probe()" function call for each model event in the enable phase, as
146 For example, from the wip sample model::
163 The probes then need to be detached at the disable phase.
/linux-6.14.4/arch/arm64/boot/dts/rockchip/
Drk3368-lion-haikou.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include "rk3368-lion.dtsi"
10 model = "Theobroma Systems RK3368-uQ7 Baseboard";
11 compatible = "tsd,rk3368-lion-haikou", "rockchip,rk3368";
18 stdout-path = "serial0:115200n8";
32 pinctrl-0 = <&module_led_pins>, <&sd_card_led_pin>;
34 sd_card_led: led-3 {
37 linux,default-trigger = "mmc0";
41 dc_12v: regulator-dc-12v {
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/linux-6.14.4/net/ipv4/
Dtcp_bbr.c21 * +---> STARTUP ----+
24 * | DRAIN ----+
27 * +---> PROBE_BW ----+
30 * | +----+ |
32 * +---- PROBE_RTT <--+
37 * A long-lived BBR flow spends the vast majority of its time remaining
41 * sample that matches or decreases its min_rtt estimate for 10 seconds, then
42 * it briefly enters PROBE_RTT to cut inflight to a minimum value to re-probe
43 * the path's two-way propagation delay (min_rtt). When exiting PROBE_RTT, if
48 * "BBR: Congestion-Based Congestion Control",
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Dtcp_westwood.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TCP Westwood+: end-to-end bandwidth estimation for TCP
10 * - Mascolo S, Casetti, M. Gerla et al.
13 * - A. Grieco, s. Mascolo
17 * - A. Dell'Aera, L. Grieco, S. Mascolo.
18 * "Linux 2.4 Implementation of Westwood+ TCP with Rate-Halving :
21 * Westwood+ employs end-to-end bandwidth measurement to set cwnd and
22 * ssthresh after packet loss. The probing phase is as the original Reno.
43 u8 reset_rtt_min; /* Reset RTT min to next RTT sample*/
65 w->bk = 0; in tcp_westwood_init()
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/linux-6.14.4/tools/perf/scripts/python/
Dgecko.py1 # gecko.py - Convert perf record output to Firefox's gecko profile format
2 # SPDX-License-Identifier: GPL-2.0
9 # perf record -a -g -F 99 sleep 60
14 # perf script gecko -F 99 -a sleep 60
32 # Add the Perf-Trace-Util library to the Python path
34 '/scripts/python/Perf-Trace-Util/lib/Perf/Trace')
48 # https://github.com/firefox-devtools/profiler/blob/53970305b51b9b472e26d7457fee1d66cd4e2737/src/ty…
49 …llow Brendan Gregg's Flamegraph convention: orange for kernel and yellow for user space by default.
53 PRODUCT = os.popen('uname -op').read().strip()
68 # https://github.com/firefox-devtools/profiler/blob/53970305b51b9b472e26d7457fee1d66cd4e2737/src/ty…
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/linux-6.14.4/drivers/gpu/drm/i915/display/
Dskl_scaler.c1 // SPDX-License-Identifier: MIT
15 * The hardware phase 0.0 refers to the center of the pixel.
16 * We want to start from the top/left edge which is phase
17 * -0.5. That matches how the hardware calculates the scaling
18 * factors (from top-left of the first pixel to bottom-right
22 * adjust that so that the chroma sample position lands in
29 * The same behaviour is observed on pre-SKL platforms as well.
31 * Theory behind the formula (note that we ignore sub-pixel
33 * s = source sample position
34 * d = destination sample position
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/linux-6.14.4/include/sound/
Demu10k1.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
16 #include <sound/pcm-indirect.h>
25 /* ------------------- DEFINES -------------------- */
33 /* FIXME? - according to the OSS driver the EMU10K1 needs a 29 bit DMA mask */
41 // This is used to define hardware bit-fields (sub-registers) by combining
44 // The non-concatenating (_NC) variant should be used directly only for
45 // sub-registers that do not follow the <register>_<field> naming pattern.
55 // Macros for manipulating values of bit-fields declared using the above macros.
59 // single sub-register at a time.
62 #define REG_MASK0(r) ((1U << REG_SIZE(r)) - 1U)
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/linux-6.14.4/tools/perf/Documentation/
Dperf-report.txt1 perf-report(1)
5 ----
6 perf-report - Read perf.data (created by perf record) and display the profile
9 --------
11 'perf report' [-i <file> | --input=file]
14 -----------
19 -------
20 -i::
21 --input=::
22 Input file name. (default: perf.data unless stdin is a fifo)
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/linux-6.14.4/kernel/time/
Dntp.c1 // SPDX-License-Identifier: GPL-2.0
26 * struct ntp_data - Structure holding all NTP related state
40 * @ntp_tick_adj: Constant boot-param configurable NTP tick adjustment (upscaled)
44 * @pps_tf: PPS phase median filter
108 * The following variables are used when a pulse-per-second (PPS) signal
122 * PPS kernel consumer compensates the whole phase error immediately.
127 if (ntpdata->time_status & STA_PPSTIME && ntpdata->time_status & STA_PPSSIGNAL) in ntp_offset_chunk()
130 return shift_right(offset, SHIFT_PLL + ntpdata->time_constant); in ntp_offset_chunk()
136 ntpdata->pps_shift = PPS_INTMIN; in pps_reset_freq_interval()
137 ntpdata->pps_intcnt = 0; in pps_reset_freq_interval()
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