Lines Matching +full:default +full:- +full:sample +full:- +full:phase
1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright 2016-2024 Analog Devices Inc.
26 #include <linux/fpga/adi-axi-common.h>
28 #include <linux/iio/buffer-dmaengine.h>
32 #include "ad3552r-hs.h"
126 guard(mutex)(&st->lock); in axi_dac_enable()
127 ret = regmap_set_bits(st->regmap, AXI_DAC_RSTN_REG, in axi_dac_enable()
136 ret = regmap_read_poll_timeout(st->regmap, AXI_DAC_DRP_STATUS_REG, in axi_dac_enable()
143 return regmap_set_bits(st->regmap, AXI_DAC_RSTN_REG, in axi_dac_enable()
151 guard(mutex)(&st->lock); in axi_dac_disable()
152 regmap_write(st->regmap, AXI_DAC_RSTN_REG, 0); in axi_dac_disable()
161 if (device_property_read_string(st->dev, "dma-names", &dma_name)) in axi_dac_request_buffer()
164 return iio_dmaengine_buffer_setup_ext(st->dev, indio_dev, dma_name, in axi_dac_request_buffer()
189 if (!st->dac_clk) { in __axi_dac_frequency_get()
190 dev_err(st->dev, "Sampling rate is 0...\n"); in __axi_dac_frequency_get()
191 return -EINVAL; in __axi_dac_frequency_get()
199 ret = regmap_read(st->regmap, reg, &raw); in __axi_dac_frequency_get()
204 *freq = DIV_ROUND_CLOSEST_ULL(raw * st->dac_clk, BIT(16)); in __axi_dac_frequency_get()
216 scoped_guard(mutex, &st->lock) { in axi_dac_frequency_get()
217 ret = __axi_dac_frequency_get(st, chan->channel, tone_2, &freq); in axi_dac_frequency_get()
234 reg = AXI_DAC_CHAN_CNTRL_3_REG(chan->channel); in axi_dac_scale_get()
236 reg = AXI_DAC_CHAN_CNTRL_1_REG(chan->channel); in axi_dac_scale_get()
238 ret = regmap_read(st->regmap, reg, &raw); in axi_dac_scale_get()
251 vals[0] *= -1; in axi_dac_scale_get()
253 vals[1] *= -1; in axi_dac_scale_get()
264 u32 reg, raw, phase; in axi_dac_phase_get() local
268 reg = AXI_DAC_CHAN_CNTRL_4_REG(chan->channel); in axi_dac_phase_get()
270 reg = AXI_DAC_CHAN_CNTRL_2_REG(chan->channel); in axi_dac_phase_get()
272 ret = regmap_read(st->regmap, reg, &raw); in axi_dac_phase_get()
277 phase = DIV_ROUND_CLOSEST_ULL((u64)raw * AXI_DAC_2_PI_MEGA, U16_MAX); in axi_dac_phase_get()
279 vals[0] = phase / MEGA; in axi_dac_phase_get()
280 vals[1] = phase % MEGA; in axi_dac_phase_get()
295 dev_err(st->dev, "Invalid frequency(%u) dac_clk(%llu)\n", in __axi_dac_frequency_set()
297 return -EINVAL; in __axi_dac_frequency_set()
307 ret = regmap_update_bits(st->regmap, reg, in __axi_dac_frequency_set()
313 return regmap_set_bits(st->regmap, AXI_DAC_CNTRL_1_REG, in __axi_dac_frequency_set()
328 guard(mutex)(&st->lock); in axi_dac_frequency_set()
329 ret = __axi_dac_frequency_set(st, chan->channel, st->dac_clk, freq, in axi_dac_frequency_set()
350 if (scale <= -2 * (int)MEGA || scale >= 2 * (int)MEGA) in axi_dac_scale_set()
351 return -EINVAL; in axi_dac_scale_set()
356 scale *= -1; in axi_dac_scale_set()
362 reg = AXI_DAC_CHAN_CNTRL_3_REG(chan->channel); in axi_dac_scale_set()
364 reg = AXI_DAC_CHAN_CNTRL_1_REG(chan->channel); in axi_dac_scale_set()
366 guard(mutex)(&st->lock); in axi_dac_scale_set()
367 ret = regmap_write(st->regmap, reg, raw); in axi_dac_scale_set()
372 ret = regmap_set_bits(st->regmap, AXI_DAC_CNTRL_1_REG, in axi_dac_scale_set()
384 int integer, frac, phase; in axi_dac_phase_set() local
392 phase = integer * MEGA + frac; in axi_dac_phase_set()
393 if (phase < 0 || phase > AXI_DAC_2_PI_MEGA) in axi_dac_phase_set()
394 return -EINVAL; in axi_dac_phase_set()
396 raw = DIV_ROUND_CLOSEST_ULL((u64)phase * U16_MAX, AXI_DAC_2_PI_MEGA); in axi_dac_phase_set()
399 reg = AXI_DAC_CHAN_CNTRL_4_REG(chan->channel); in axi_dac_phase_set()
401 reg = AXI_DAC_CHAN_CNTRL_2_REG(chan->channel); in axi_dac_phase_set()
403 guard(mutex)(&st->lock); in axi_dac_phase_set()
404 ret = regmap_update_bits(st->regmap, reg, AXI_DAC_CHAN_CNTRL_2_PHASE, in axi_dac_phase_set()
410 ret = regmap_set_bits(st->regmap, AXI_DAC_CNTRL_1_REG, in axi_dac_phase_set()
437 default: in axi_dac_ext_info_set()
438 return -EOPNOTSUPP; in axi_dac_ext_info_set()
451 private - AXI_DAC_FREQ_TONE_1); in axi_dac_ext_info_get()
455 private - AXI_DAC_SCALE_TONE_1); in axi_dac_ext_info_get()
459 private - AXI_DAC_PHASE_TONE_1); in axi_dac_ext_info_get()
460 default: in axi_dac_ext_info_get()
461 return -EOPNOTSUPP; in axi_dac_ext_info_get()
480 if (chan->type != IIO_ALTVOLTAGE) in axi_dac_extend_chan()
481 return -EINVAL; in axi_dac_extend_chan()
482 if (st->reg_config & AXI_DAC_CONFIG_DDS_DISABLE) in axi_dac_extend_chan()
486 chan->ext_info = axi_dac_ext_info; in axi_dac_extend_chan()
498 return regmap_update_bits(st->regmap, in axi_dac_data_source_set()
503 return regmap_update_bits(st->regmap, in axi_dac_data_source_set()
508 return regmap_update_bits(st->regmap, in axi_dac_data_source_set()
512 default: in axi_dac_data_source_set()
513 return -EINVAL; in axi_dac_data_source_set()
525 return -EINVAL; in axi_dac_set_sample_rate()
526 if (st->reg_config & AXI_DAC_CONFIG_DDS_DISABLE) in axi_dac_set_sample_rate()
530 guard(mutex)(&st->lock); in axi_dac_set_sample_rate()
533 * about the interface sample rate. Hence, just update our internal in axi_dac_set_sample_rate()
536 * sample rate. in axi_dac_set_sample_rate()
538 if (!st->dac_clk) { in axi_dac_set_sample_rate()
539 st->dac_clk = sample_rate; in axi_dac_set_sample_rate()
553 st->dac_clk = sample_rate; in axi_dac_set_sample_rate()
564 return regmap_read(st->regmap, reg, readval); in axi_dac_reg_access()
566 return regmap_write(st->regmap, reg, writeval); in axi_dac_reg_access()
573 return regmap_clear_bits(st->regmap, AXI_DAC_CNTRL_2_REG, in axi_dac_ddr_enable()
581 return regmap_set_bits(st->regmap, AXI_DAC_CNTRL_2_REG, in axi_dac_ddr_disable()
590 ret = regmap_read_poll_timeout(st->regmap, in axi_dac_data_stream_enable()
597 return regmap_set_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG, in axi_dac_data_stream_enable()
605 return regmap_clear_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG, in axi_dac_data_stream_disable()
614 return -EINVAL; in axi_dac_data_transfer_addr()
617 * Sample register address, when the DAC is configured, or stream in axi_dac_data_transfer_addr()
620 return regmap_update_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG, in axi_dac_data_transfer_addr()
631 switch (data->type) { in axi_dac_data_format_set()
633 return regmap_clear_bits(st->regmap, AXI_DAC_CNTRL_2_REG, in axi_dac_data_format_set()
635 default: in axi_dac_data_format_set()
636 return -EINVAL; in axi_dac_data_format_set()
659 ret = regmap_write(st->regmap, AXI_DAC_CUSTOM_WR_REG, ival); in __axi_dac_bus_reg_write()
664 ret = regmap_set_bits(st->regmap, AXI_DAC_CNTRL_2_REG, in __axi_dac_bus_reg_write()
667 ret = regmap_clear_bits(st->regmap, AXI_DAC_CNTRL_2_REG, in __axi_dac_bus_reg_write()
672 ret = regmap_update_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG, in __axi_dac_bus_reg_write()
678 ret = regmap_update_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG, in __axi_dac_bus_reg_write()
684 ret = regmap_read_poll_timeout(st->regmap, in __axi_dac_bus_reg_write()
688 if (ret == -ETIMEDOUT) in __axi_dac_bus_reg_write()
689 dev_err(st->dev, "AXI read timeout\n"); in __axi_dac_bus_reg_write()
692 return regmap_clear_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG, in __axi_dac_bus_reg_write()
701 guard(mutex)(&st->lock); in axi_dac_bus_reg_write()
711 guard(mutex)(&st->lock); in axi_dac_bus_reg_read()
722 return regmap_read(st->regmap, AXI_DAC_CUSTOM_RD_REG, val); in axi_dac_bus_reg_read()
736 .bus_sample_data_clock_hz = st->dac_clk_rate, in axi_dac_create_platform_device()
739 .parent = st->dev, in axi_dac_create_platform_device()
752 return devm_add_action_or_reset(st->dev, axi_dac_child_remove, pdev); in axi_dac_create_platform_device()
783 .name = "axi-dac",
788 .name = "axi-ad3552r",
807 st = devm_kzalloc(&pdev->dev, sizeof(*st), GFP_KERNEL); in axi_dac_probe()
809 return -ENOMEM; in axi_dac_probe()
811 st->info = device_get_match_data(&pdev->dev); in axi_dac_probe()
812 if (!st->info) in axi_dac_probe()
813 return -ENODEV; in axi_dac_probe()
814 clk = devm_clk_get_enabled(&pdev->dev, "s_axi_aclk"); in axi_dac_probe()
816 /* Backward compat., old fdt versions without clock-names. */ in axi_dac_probe()
817 clk = devm_clk_get_enabled(&pdev->dev, NULL); in axi_dac_probe()
819 return dev_err_probe(&pdev->dev, PTR_ERR(clk), in axi_dac_probe()
823 if (st->info->has_dac_clk) { in axi_dac_probe()
826 dac_clk = devm_clk_get_enabled(&pdev->dev, "dac_clk"); in axi_dac_probe()
828 return dev_err_probe(&pdev->dev, PTR_ERR(dac_clk), in axi_dac_probe()
832 st->dac_clk_rate = clk_get_rate(dac_clk) / 2; in axi_dac_probe()
839 st->dev = &pdev->dev; in axi_dac_probe()
840 st->regmap = devm_regmap_init_mmio(&pdev->dev, base, in axi_dac_probe()
842 if (IS_ERR(st->regmap)) in axi_dac_probe()
843 return dev_err_probe(&pdev->dev, PTR_ERR(st->regmap), in axi_dac_probe()
850 ret = regmap_write(st->regmap, AXI_DAC_RSTN_REG, 0); in axi_dac_probe()
854 ret = regmap_read(st->regmap, ADI_AXI_REG_VERSION, &ver); in axi_dac_probe()
859 ADI_AXI_PCORE_VER_MAJOR(st->info->version)) { in axi_dac_probe()
860 dev_err(&pdev->dev, in axi_dac_probe()
862 ADI_AXI_PCORE_VER_MAJOR(st->info->version), in axi_dac_probe()
863 ADI_AXI_PCORE_VER_MINOR(st->info->version), in axi_dac_probe()
864 ADI_AXI_PCORE_VER_PATCH(st->info->version), in axi_dac_probe()
868 return -ENODEV; in axi_dac_probe()
872 ret = regmap_read(st->regmap, AXI_DAC_CONFIG_REG, &st->reg_config); in axi_dac_probe()
877 * In some designs, setting the R1_MODE bit to 0 (which is the default in axi_dac_probe()
880 * Multiple-Input and Multiple-Output (MIMO). As most of the times we in axi_dac_probe()
881 * want independent channels let's override the core's default value and in axi_dac_probe()
884 ret = regmap_set_bits(st->regmap, AXI_DAC_CNTRL_2_REG, in axi_dac_probe()
889 mutex_init(&st->lock); in axi_dac_probe()
891 ret = devm_iio_backend_register(&pdev->dev, st->info->backend_info, st); in axi_dac_probe()
893 return dev_err_probe(&pdev->dev, ret, in axi_dac_probe()
896 device_for_each_child_node_scoped(&pdev->dev, child) { in axi_dac_probe()
899 if (!st->info->has_child_nodes) in axi_dac_probe()
900 return dev_err_probe(&pdev->dev, -EINVAL, in axi_dac_probe()
901 "invalid fdt axi-dac compatible."); in axi_dac_probe()
906 return dev_err_probe(&pdev->dev, ret, in axi_dac_probe()
909 return dev_err_probe(&pdev->dev, -EINVAL, in axi_dac_probe()
914 return dev_err_probe(&pdev->dev, -EINVAL, in axi_dac_probe()
918 dev_info(&pdev->dev, "AXI DAC IP core (%d.%.2d.%c) probed\n", in axi_dac_probe()
939 { .compatible = "adi,axi-dac-9.1.b", .data = &dac_generic },
940 { .compatible = "adi,axi-ad3552r", .data = &dac_ad3552r },
947 .name = "adi-axi-dac",