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/linux-6.14.4/Documentation/devicetree/bindings/mmc/
Dmmc-pwrseq-simple.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-pwrseq-simple.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <[email protected]>
19 const: mmc-pwrseq-simple
21 reset-gpios:
28 They will be de-asserted right after the power has been provided to the
33 description: Handle for the entry in clock-names.
35 clock-names:
[all …]
/linux-6.14.4/drivers/hwmon/
Dsfctemp.c1 // SPDX-License-Identifier: GPL-2.0
19 * TempSensor reset. The RSTN can be de-asserted once the analog core has
21 * 0:reset 1:de-assert
27 * Tpu(min 50us) after PD is de-asserted. RSTN should be held low until the
41 * Temp(C)=DOUT*Y/4094 - K
65 writel(SFCTEMP_PD, sfctemp->regs); in sfctemp_power_up()
68 writel(0, sfctemp->regs); in sfctemp_power_up()
72 /* de-assert reset */ in sfctemp_power_up()
73 writel(SFCTEMP_RSTN, sfctemp->regs); in sfctemp_power_up()
79 writel(SFCTEMP_PD, sfctemp->regs); in sfctemp_power_down()
[all …]
/linux-6.14.4/drivers/clk/qcom/
Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/clk-provider.h>
17 #include "clk-pll.h"
31 ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val); in clk_pll_enable()
40 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, in clk_pll_enable()
47 * de-asserting the reset. Delay 10us just to be safe. in clk_pll_enable()
51 /* De-assert active-low PLL reset. */ in clk_pll_enable()
52 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N, in clk_pll_enable()
61 return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL, in clk_pll_enable()
71 regmap_read(pll->clkr.regmap, pll->mode_reg, &val); in clk_pll_disable()
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Dclk-hfpll.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/clk-provider.h>
12 #include "clk-regmap.h"
13 #include "clk-hfpll.h"
23 struct hfpll_data const *hd = h->d; in __clk_hfpll_init_once()
24 struct regmap *regmap = h->clkr.regmap; in __clk_hfpll_init_once()
26 if (likely(h->init_done)) in __clk_hfpll_init_once()
30 if (hd->config_val) in __clk_hfpll_init_once()
31 regmap_write(regmap, hd->config_reg, hd->config_val); in __clk_hfpll_init_once()
32 regmap_write(regmap, hd->m_reg, 0); in __clk_hfpll_init_once()
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/linux-6.14.4/Documentation/devicetree/bindings/net/bluetooth/
Dnxp,88w8987-bt.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/bluetooth/nxp,88w8987-bt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 This binding describes UART-attached NXP bluetooth chips. These chips
11 are dual-radio chips supporting WiFi and Bluetooth. The bluetooth
12 works on standard H4 protocol over 4-wire UART. The RTS and CTS lines
14 asserts break signal over UART-TX line to put the chip into power save
15 state. De-asserting break wakes up the BT chip.
18 - Neeraj Sanjay Kale <[email protected]>
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/linux-6.14.4/drivers/gpu/drm/msm/hdmi/
Dhdmi_pll_8960.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk-provider.h>
27 * configuration into common-clock-framework.
239 writel(data, pll->mmio + reg); in pll_write()
244 return readl(pll->mmio + reg); in pll_read()
249 return platform_get_drvdata(pll->pdev); in pll_get_phy()
266 /* Wait for a short time before de-asserting in hdmi_pll_enable()
269 * to assert and de-assert. in hdmi_pll_enable()
273 /* De-assert PLL S/W reset */ in hdmi_pll_enable()
282 * Wait for a short time before de-asserting to allow the hardware to in hdmi_pll_enable()
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/linux-6.14.4/drivers/reset/
Dreset-brcmstb.c1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/reset-controller.h>
46 writel_relaxed(SW_INIT_BIT(id), priv->base + off + SW_INIT_SET); in brcmstb_reset_assert()
57 writel_relaxed(SW_INIT_BIT(id), priv->base + off + SW_INIT_CLEAR); in brcmstb_reset_deassert()
58 /* Maximum reset delay after de-asserting a line and seeing block in brcmstb_reset_deassert()
73 return readl_relaxed(priv->base + off + SW_INIT_STATUS) & in brcmstb_reset_status()
85 struct device *kdev = &pdev->dev; in brcmstb_reset_probe()
91 return -ENOMEM; in brcmstb_reset_probe()
93 priv->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in brcmstb_reset_probe()
94 if (IS_ERR(priv->base)) in brcmstb_reset_probe()
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/linux-6.14.4/drivers/remoteproc/
Dqcom_q6v5_adsp.c1 // SPDX-License-Identifier: GPL-2.0
125 struct device *dev = adsp->dev; in qcom_rproc_pds_attach()
133 if (dev->pm_domain) in qcom_rproc_pds_attach()
139 ret = dev_pm_domain_attach_list(dev, &pd_data, &adsp->pd_list); in qcom_rproc_pds_attach()
150 struct device *dev = adsp->dev; in qcom_rproc_pds_detach()
151 struct dev_pm_domain_list *pds = adsp->pd_list; in qcom_rproc_pds_detach()
155 if (dev->pm_domain || pds) in qcom_rproc_pds_detach()
156 pm_runtime_disable(adsp->dev); in qcom_rproc_pds_detach()
161 struct device *dev = adsp->dev; in qcom_rproc_pds_enable()
162 struct dev_pm_domain_list *pds = adsp->pd_list; in qcom_rproc_pds_enable()
[all …]
/linux-6.14.4/drivers/cpufreq/
Dgx-suspmod.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * (C) 2002 Hiroshi Miura <miura@da-cha.org>
10 * software is provided AS-IS with no warranties.
19 * Suspend Modulation works by asserting and de-asserting the SUSP# pin
20 * to CPU(GX1/GXLV) for configurable durations. When asserting SUSP#
28 * 32us intervals which the SUSP# pin is asserted(ON)/de-asserted(OFF)
35 * F_eff = Fgx * ----------------------
43 * on_duration = off_duration * (stock_freq - freq) / freq
46 * on_duration = DURATION - off_duration
48 *---------------------------------------------------------------------------
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/linux-6.14.4/arch/arm/mach-omap2/
Dprminst44xx.c1 // SPDX-License-Identifier: GPL-2.0-only
18 #include "prcm-common.h"
23 #include "prm-regbits-44xx.h"
34 * omap_prm_base_init - Populates the prm partitions
75 /* Read-modify-write a register in PRM. Caller must lock */
90 * omap4_prminst_is_hardreset_asserted - read the HW reset line state of
97 * -EINVAL upon parameter error.
112 * omap4_prminst_assert_hardreset - assert the HW reset line of a submodule
118 * IP. These modules may have multiple hard-reset lines that reset
120 * place the submodule into reset. Returns 0 upon success or -EINVAL
[all …]
Dprm2xxx_3xxx.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2010-2011 Texas Instruments, Inc.
18 #include "prm-regbits-24xx.h"
22 * omap2_prm_is_hardreset_asserted - read the HW reset line state of
31 * -EINVAL if called while running on a non-OMAP2/3 chip.
40 * omap2_prm_assert_hardreset - assert the HW reset line of a submodule
48 * IP. These modules may have multiple hard-reset lines that reset
50 * place the submodule into reset. Returns 0 upon success or -EINVAL
64 * omap2_prm_deassert_hardreset - deassert a submodule hardreset line and wait
75 * IP. These modules may have multiple hard-reset lines that reset
[all …]
Dprm33xx.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
17 #include "prm-regbits-33xx.h"
31 /* Read-modify-write a register in PRM. Caller must lock */
45 * am33xx_prm_is_hardreset_asserted - read the HW reset line state of
54 * -EINVAL upon parameter error.
69 * am33xx_prm_assert_hardreset - assert the HW reset line of a submodule
77 * IP. These modules may have multiple hard-reset lines that reset
79 * place the submodule into reset. Returns 0 upon success or -EINVAL
93 * am33xx_prm_deassert_hardreset - deassert a submodule hardreset line and
[all …]
/linux-6.14.4/arch/arm/mach-sunxi/
Dmc_smp.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018 Chen-Yu Tsai
5 * Chen-Yu Tsai <[email protected]>
7 * arch/arm/mach-sunxi/mc_smp.c
9 * Based on Allwinner code, arch/arm/mach-exynos/mcpm-exynos.c, and
10 * arch/arm/mach-hisi/platmcpm.c
14 #include <linux/arm-cci.h>
19 #include <linux/irqchip/arm-gic.h>
70 /* R_CPUCFG registers, specific to sun8i-a83t */
110 is_compatible = of_device_is_compatible(node, "arm,cortex-a15"); in sunxi_core_is_cortex_a15()
[all …]
/linux-6.14.4/drivers/i2c/
Di2c-smbus.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * i2c-smbus.c - SMBus extensions to the I2C protocol
6 * Copyright (C) 2010-2019 Jean Delvare <jdelvare@suse.de>
13 #include <linux/i2c-smbus.h>
40 if (!client || client->addr != data->addr) in smbus_do_alert()
42 if (client->flags & I2C_CLIENT_TEN) in smbus_do_alert()
50 if (client->dev.driver) { in smbus_do_alert()
51 driver = to_i2c_driver(client->dev.driver); in smbus_do_alert()
52 if (driver->alert) { in smbus_do_alert()
54 driver->alert(client, data->type, data->data); in smbus_do_alert()
[all …]
/linux-6.14.4/drivers/pci/controller/
Dpcie-mediatek-gen3.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/clk-provider.h>
78 #define PCIE_MSI_ENABLE GENMASK(PCIE_MSI_SET_NUM + 8 - 1, 8)
82 GENMASK(PCIE_INTX_SHIFT + PCI_NUM_INTX - 1, PCIE_INTX_SHIFT)
86 #define PCIE_MSI_SET_ENABLE GENMASK(PCIE_MSI_SET_NUM - 1, 0)
120 (((((size) - 1) << 1) & GENMASK(6, 1)) | PCIE_ATR_EN)
148 * struct mtk_gen3_pcie_pdata - differentiate between host generations
163 * struct mtk_msi_set - MSI information for each set
175 * struct mtk_gen3_pcie - PCIe port information
195 * @soc: pointer to SoC-dependent operations
[all …]
Dpcie-rockchip-ep.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Simon Xue <xxm@rock-chips.com>
18 #include <linux/pci-epc.h>
20 #include <linux/pci-epf.h>
24 #include "pcie-rockchip.h"
27 * struct rockchip_pcie_ep - private data for PCIe endpoint controller driver
81 int num_pass_bits = fls64(pci_addr ^ (pci_addr + size - 1)); in rockchip_pcie_ep_ob_atu_num_bits()
98 addr0 = ((num_pass_bits - 1) & PCIE_CORE_OB_REGION_ADDR0_NUM_BITS) | in rockchip_pcie_prog_ep_ob_atu()
119 struct rockchip_pcie *rockchip = &ep->rockchip; in rockchip_pcie_ep_write_header()
[all …]
/linux-6.14.4/drivers/clk/
Dclk-gpio.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2013 - 2014 Texas Instruments Incorporated - https://www.ti.com
7 * Sergej Sawazki <ce3a@gmx.de>
12 #include <linux/clk-provider.h>
26 * prepare - clk_(un)prepare are functional and control a gpio that can sleep
27 * enable - clk_enable and clk_disable are functional & control
28 * non-sleeping gpio
29 * rate - inherits rate from parent. No clk_set_rate support
30 * parent - fixed parent. No clk_set_parent support
34 * struct clk_gpio - gpio gated clock
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/linux-6.14.4/drivers/clk/tegra/
Dclk.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk-provider.h>
16 #include <linux/reset-controller.h>
35 /* Handlers for SoC-specific reset lines */
121 return -EINVAL; in tegra_clk_rst_assert()
135 return -EINVAL; in tegra_clk_rst_deassert()
200 * All non-boot peripherals will be in reset state on resume. in tegra_clk_periph_resume()
201 * Wait for 5us of reset propagation delay before de-asserting in tegra_clk_periph_resume()
218 return -ENOMEM; in tegra_clk_periph_ctx_init()
262 for (; dup_list->clk_id < clk_max; dup_list++) { in tegra_init_dup_clks()
[all …]
/linux-6.14.4/drivers/input/touchscreen/
Dauo-pixcir-ts.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for AUO in-cell touchscreens
5 * Copyright (c) 2011 Heiko Stuebner <heiko@sntech.de>
7 * loosely based on auo_touch.c from Dell Streak vendor-kernel
87 * sleep: scan speed 10Hz can be auto-activated, wakeup on 1st touch
141 struct i2c_client *client = ts->client; in auo_pixcir_collect_data()
150 dev_err(&client->dev, "failed to read coordinate, %d\n", ret); in auo_pixcir_collect_data()
158 dev_err(&client->dev, "could not read touch area, %d\n", ret); in auo_pixcir_collect_data()
168 if (point[i].coord_x > ts->x_max || in auo_pixcir_collect_data()
169 point[i].coord_y > ts->y_max) { in auo_pixcir_collect_data()
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/linux-6.14.4/Documentation/scsi/
DChangeLog.megaraid1 Release Date : Thu Nov 16 15:32:35 EST 2006 -
9 and re-initialize its internal RAID structure.
14 2. Authors email-id domain name changed from lsil.com to lsi.com.
17 Release Date : Fri May 19 09:31:45 EST 2006 - Seokmann Ju <[email protected]>
23 Root Cause: the driver registered controllers as 64-bit DMA capable
26 identifying 64-bit DMA capable controllers.
28 > -----Original Message-----
31 > To: linux-[email protected]; Kolli, Neela; Mukker, Atul;
86 issue on 64-bit platform.
93 > -----Original Message-----
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/linux-6.14.4/drivers/usb/host/
Dehci-fsl.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2005-2009 MontaVista Software, Inc.
9 * Jerry Huang <Chang-[email protected]> and
29 #include "ehci-fsl.h"
32 #define DRV_NAME "fsl-ehci"
40 * fsl_ehci_drv_probe - initialize FSL-based HCDs
56 pr_debug("initializing FSL-SOC USB Controller\n"); in fsl_ehci_drv_probe()
59 pdata = dev_get_platdata(&pdev->dev); in fsl_ehci_drv_probe()
61 dev_err(&pdev->dev, in fsl_ehci_drv_probe()
62 "No platform data for %s.\n", dev_name(&pdev->dev)); in fsl_ehci_drv_probe()
[all …]
/linux-6.14.4/LICENSES/dual/
DMPL-1.11 Valid-License-Identifier: MPL-1.1
2 SPDX-URL: https://spdx.org/licenses/MPL-1.1.html
3 Usage-Guide:
4 Do NOT use. The MPL-1.1 is not GPL2 compatible. It may only be used for
5 dual-licensed files where the other license is GPL2 compatible.
11 SPDX-License-Identifier: MPL-1.1
12 License-Text:
17 ---------------
81 appropriate decompression or de-archiving software is widely available
98 The Initial Developer hereby grants You a world-wide, royalty-free,
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/linux-6.14.4/Documentation/admin-guide/media/
Dbttv.rst1 .. SPDX-License-Identifier: GPL-2.0
8 ----------------------
12 ./scripts/config -e PCI
13 ./scripts/config -m I2C
14 ./scripts/config -m INPUT
15 ./scripts/config -m MEDIA_SUPPORT
16 ./scripts/config -e MEDIA_PCI_SUPPORT
17 ./scripts/config -e MEDIA_ANALOG_TV_SUPPORT
18 ./scripts/config -e MEDIA_DIGITAL_TV_SUPPORT
19 ./scripts/config -e MEDIA_RADIO_SUPPORT
[all …]
/linux-6.14.4/arch/x86/kernel/
Dsmpboot.c1 // SPDX-License-Identifier: GPL-2.0-or-later
13 * Pentium Pro and Pentium-II/Xeon MP machines.
19 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
32 * Martin J. Bligh : Added support for multi-quad systems
86 #include <asm/intel-family.h>
88 #include <asm/spec-ctrl.h>
92 #include <asm/spec-ctrl.h>
164 if (!--smpboot_warm_reset_vector_count) { in smpboot_restore_warm_reset_vector()
242 * 32-bit specific. 64-bit reaches this code with the correct page in start_secondary()
273 * synchronization state to ALIVE and spin-waits for the control CPU to in start_secondary()
[all …]
/linux-6.14.4/drivers/cdx/controller/
Dmc_cdx_pcol.h1 /* SPDX-License-Identifier: GPL-2.0
6 * Copyright (C) 2022-2023, Advanced Micro Devices, Inc.
22 * | | \--- Response
23 * | \------- Error
24 * \------------------------------ Resync (always set)
76 * - To advance a shared memory request if XFLAGS_EVREQ was set
77 * - As a notification (link state, i2c event), controlled
89 * - LEVEL==INFO Command succeeded
90 * - LEVEL==ERR Command failed
101 * non-existent MCDI command MC_CMD_DEBUG_LOG.
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