Searched +full:d3 +full:- +full:timer (Results 1 – 25 of 289) sorted by relevance
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25 fs-extra:34 node-watch:43 /@braintree/sanitize-[email protected]:44 …resolution: {integrity: sha512-s3jaWicZd0pkP0jf5ysyHUI/RE7MHos6qlToFcGWXVp+ykHOy77OUMrfbgJ9it2C5bo…48 …resolution: {integrity: sha512-j+gKExEuLmKwvz3OgROXtrJ2UG2x8Ch2YZUxahh+s1F2HZ+wAceUNLkvy6zKCPVRkU+…52 …resolution: {integrity: sha512-AZkcAA5vnN/v4PDqKyMR5lx7hZttPDgClv83E//FMNhR2TMcLUhfRUBHCmSl0oi9zMg…56 …resolution: {integrity: sha512-YyFaikqM5sH0ziFZCN3xDC7zeGaB/d0IUb9CATugHWbd1FRFwWwt4ld4OYMPWu5a3Xe…60 …resolution: {integrity: sha512-j9ednRT81vYJ9OfVuXG6ERSTdEL1xVsNgqpkxMsbIabzSo3goCjDIveeGv5d03om39M…64 …resolution: {integrity: sha512-lljVXpqXebpsijW71PZaCYeIcE5on1w5DlQy5WH6GLbFryLUrBD4932W/E2BSpfRJWs…71 …resolution: {integrity: sha512-Ddb+kVXlXst9d+R9PfTIxh1EdNkgoRe5tOX6t01f1lYWOvJnSPDBlG241QLzcyPdoNT…[all …]
2 * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.4 * SPDX-License-Identifier: BSD-3-Clause24 * Bit 0: ARM realtime core (Cortex-R7) master port25 * 0: Non-Secure33 * Bit19: AXI-Bus (Main Memory domain AXI) slave ports52 * 1: Reserved[R-Car E3/D3]55 * 1: Reserved[R-Car E3/D3]78 * Bit27: System Timer (SCMT) slave ports80 * Bit26: System Watchdog Timer (SWDT) slave ports126 * Bit19: AXI-Bus (Main Memory domain AXI) slave ports.[all …]
2 * Copyright (c) 2015-2023, Renesas Electronics Corporation. All rights reserved.4 * SPDX-License-Identifier: BSD-3-Clause24 * Bit 0: ARM realtime core (Cortex-R7) master port25 * 0: Non-Secure33 * Bit19: AXI-Bus (Main Memory domain AXI) slave ports52 * 1: Reserved[R-Car E3/D3]55 * 1: Reserved[R-Car E3/D3]78 * Bit27: System Timer (SCMT) slave ports80 * Bit26: System Watchdog Timer (SWDT) slave ports128 * Bit19: AXI-Bus (Main Memory domain AXI) slave ports.[all …]
1 /* SPDX-License-Identifier: GPL-2.0-or-later */30 /* 250ms in "Timer" units (i.e. 100ns increments) */39 /* Dynamically-assigned NVVDD PG GPIO, set in _INI in SSDT */61 /* Defer GC6 entry / exit until D3-cold request */67 /* GCOFF Timer */115 /* Ramp down FBVDD - TODO: Remove Agah when board is dropped */140 /* Re-enable PCIe SRCCLK# */157 /* Ramp up FBVDD - TODO: Remove Agah when board is dropped */172 Local0--191 Local0 = Timer - GCOT[all …]
1 /* SPDX-License-Identifier: GPL-2.0-or-later */37 /* 250ms in "Timer" units (i.e. 100ns increments) */48 * - The PG pin for the NVVDD VR moved from GPP_E16 to GPP_E3.49 * - The enable pin for the PEXVDD VR moved from GPP_E10 to GPP_F1255 /* Dynamically-assigned NVVDD PG GPIO, set in _INI in SSDT */77 /* Defer GC6 entry / exit until D3-cold request */83 /* GCOFF Timer */131 /* Ramp down FBVDD - TODO: Remove Agah when board is dropped */164 /* Re-enable PCIe SRCCLK# */181 /* Ramp up FBVDD - TODO: Remove Agah when board is dropped */[all …]
9 "d3": "7.8.5" string12 "@typescript-eslint/eslint-plugin": "5.59.6",13 "@typescript-eslint/parser": "5.59.6",15 "eslint-config-prettier": "8.8.0",16 "npm-run-all": "4.1.5",19 "stylelint-config-standard": "33.0.0",23 "node_modules/@aashutoshrathi/word-wrap": {25 "resolved": "https://registry.npmjs.org/@aashutoshrathi/word-wrap/-/word-wrap-1.2.6.tgz",26 …"integrity": "sha512-1Yjs2SvM8TflER/OD3cOjhWWOZb58A2t7wpE2S9XfBYTiIl+XFhQG2bjy4Pu1I+EAlCNUzRDYDdFw…32 "node_modules/@babel/code-frame": {[all …]
2 * Copyright (c) 2015-2023, Renesas Electronics Corporation. All rights reserved.4 * SPDX-License-Identifier: BSD-3-Clause35 #define DRAM1_NS_SIZE (DRAM1_SIZE - DRAM1_NS_BASE)49 RCAR_SHARED_MEM_SIZE - 0x100)86 #define RCAR_BL31_LOG_MAX (RCAR_BL31_LOG_SIZE - \120 /* Timer control */127 #define RCAR_CA53WUPCR U(0xE6151010) /* Wake-up control A53 */128 #define RCAR_CA57WUPCR U(0xE6152010) /* Wake-up control A57 */135 #define RCAR_WUPMSKCA57 U(0xE6180014) /* Wake-up mask A57 */136 #define RCAR_WUPMSKCA53 U(0xE6180018) /* Wake-up mask A53 */[all …]
2 * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.4 * SPDX-License-Identifier: BSD-3-Clause35 #define DRAM1_NS_SIZE (DRAM1_SIZE - DRAM1_NS_BASE)49 RCAR_SHARED_MEM_SIZE - 0x100)86 #define RCAR_BL31_LOG_MAX (RCAR_BL31_LOG_SIZE - \120 /* Timer control */127 #define RCAR_CA53WUPCR U(0xE6151010) /* Wake-up control A53 */128 #define RCAR_CA57WUPCR U(0xE6152010) /* Wake-up control A57 */135 #define RCAR_WUPMSKCA57 U(0xE6180014) /* Wake-up mask A57 */136 #define RCAR_WUPMSKCA53 U(0xE6180018) /* Wake-up mask A53 */[all …]
4 * Use of this source code is governed by a BSD-style license that can be15 #include "tools/timer/TimeUtils.h"42 canvas->drawLine(0, baseline, fSize.width(), baseline, paint); in draw()45 ctm.setRotate(fRotate); // d3 rotate takes degrees in draw()48 canvas->concat(ctm); in draw()50 // d3 by default anchors text around the middle in draw()53 …canvas->drawSimpleText(text, strlen(text), SkTextEncoding::kUTF8, -bounds.centerX(), -bounds.cente… in draw()59 double t = TimeUtils::PingPong(1e-9 * nanos, 20, 0, 0, maxt); // d3 t is in milliseconds in animate()61 fTranslate.set(sin(t / 3000) - t * fSize.width() * 0.7 / maxt, sin(t / 999) / t); in animate()62 fScale = 4.5 - std::sqrt(t) / 99; in animate()
77 UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN)88 /** Offset 0x0040 - Logo Pointer93 /** Offset 0x0044 - Logo Size98 /** Offset 0x0048 - Blt Buffer Address103 /** Offset 0x004C - Blt Buffer Size109 /** Offset 0x0050 - Graphics Configuration Ptr114 /** Offset 0x0054 - Enable Device 4120 /** Offset 0x0055 - Show SPI controller126 /** Offset 0x0056 - Reserved130 /** Offset 0x0058 - MicrocodeRegionBase[all …]
77 UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN)88 /** Offset 0x0040 - Logo Pointer93 /** Offset 0x0048 - Logo Size98 /** Offset 0x004C - Reserved102 /** Offset 0x0050 - Blt Buffer Address107 /** Offset 0x0058 - Blt Buffer Size113 /** Offset 0x0060 - Graphics Configuration Ptr118 /** Offset 0x0068 - Enable Device 4124 /** Offset 0x0069 - Show SPI controller130 /** Offset 0x006A - Reserved[all …]
4 issues in each release of Trusted Firmware-A.6 ## 2.6 (2021-11-22)10 - **Architecture**12 - **Activity Monitors Extension (FEAT_AMU)**14 - The public AMU API has been reduced to enablement only17 …s ([b4b726e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b4b726ea…19 - The `PLAT_AMU_GROUP1_COUNTERS_MASK` platform definition20 has been removed. Platforms should specify per-core AMU counter masks21 via FCONF or a platform-specific mechanism going forward.23 …` ([6c8dda1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6c8dda19…[all …]
6 * Copyright 1997--1999 Martin Mares <[email protected]>42 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */50 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */113 /* 0x35-0x3b are reserved */119 /* Header type 1 (PCI-to-PCI bridges) */123 #define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */147 /* 0x35-0x3b is reserved */149 /* 0x3c-0x3d are same as for htype 0 */166 #define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */180 /* 0x3c-0x3d are same as for htype 0 */[all …]
5 (tool "Eeschema 4.0.4+e1-6308~48~ubuntu14.04.1-stable")8 (title "WALT Latency Timer")20 (footprint Housings_DIP:DIP-28_W15.24mm)43 (comp (ref D3)57 (footprint Housings_DFN_QFN:QFN-16-1EP_4x4mm_Pitch0.65mm)63 (footprint TO_SOT_Packages_SMD:SOT-23-5)142 (fp QFN-16*))206 (fp LED-3MM)207 (fp LED-5MM)208 (fp LED-10MM)[all …]
10 LIBS:adc-dac22 LIBS:digital-audio33 LIBS:WALTsm-cache37 encoding utf-839 Title "WALT Latency Timer"54 F 2 "Housings_DIP:DIP-28_W15.24mm" V 2950 2750 50 0001 C CNN57 1 0 0 -1 68 -1 0 0 1 79 -1 0 0 1 90 1 0 0 -1 [all …]
1 ## SPDX-License-Identifier: GPL-2.0-only60 OCP Timer need to be disabled in SCS UFS IOSF Bridge to67 LTR needs to be disqualified for UFS in D3 to ensure PMC
77 UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN)88 /** Offset 0x0040 - Logo Pointer93 /** Offset 0x0044 - Logo Size98 /** Offset 0x0048 - Blt Buffer Address103 /** Offset 0x004C - Blt Buffer Size109 /** Offset 0x0050 - Graphics Configuration Ptr114 /** Offset 0x0054 - Enable Device 4120 /** Offset 0x0055 - Show SPI controller130 /** Offset 0x0058 - MicrocodeRegionBase135 /** Offset 0x005C - MicrocodeRegionSize[all …]
3 Copyright (c) 2022 - 2024, Intel Corporation. All rights reserved.<BR>77 UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN)88 /** Offset 0x0040 - Logo Pointer93 /** Offset 0x0044 - Logo Size98 /** Offset 0x0048 - Blt Buffer Address103 /** Offset 0x004C - Blt Buffer Size109 /** Offset 0x0050 - Graphics Configuration Ptr114 /** Offset 0x0054 - Enable Device 4120 /** Offset 0x0055 - Show SPI controller126 /** Offset 0x0056 - Reserved[all …]
4 ## _0-96 * _XXX - An underscore followed by 3 uppercase letters will typically be10 * 2FA - [**Two-factor Authentication**](https://en.wikipedia.org/wiki/Multi-factor_authentication)11 * 4G - In coreboot, this typically refers to the 4 gibibyte boundary of 32-bit addressable memory s…13 * 5G - Telecommunication: [**Fifth-Generation Cellular Network**](https://en.wikipedia.org/wiki/5G)16 * ABI - [**Application Binary Interface**](https://en.wikipedia.org/wiki/Application_binary_interfa…17 * ABL - AMD: AGESA BootLoader (or AMD BootLoader) - The portion of the AMD processor20 * AC - Electricity: [**Alternating Current**](https://en.wikipedia.org/wiki/Alternating_current)21 * Ack - Acknowledgment / Acknowledged23 * ACP - [**Average CPU power**](https://en.wikipedia.org/wiki/Thermal_design_power)[all …]
23 '@codemirror/theme-one-dark':41 '@types/color-convert':62 '@types/w3c-web-usb':68 color-convert:71 devtools-protocol:89 jsbn-rsa:95 noice-json-rpc:104 protobufjs-cli:116 vega-lite:133 '@rollup/plugin-commonjs':[all …]
1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */5 * Copyright 1997--1999 Martin Mares <[email protected]>25 * Conventional PCI and PCI-X Mode 1 devices have 256 bytes of26 * configuration space. PCI-X Mode 2 and PCIe devices have 4096 bytes of50 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */59 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */83 #define PCI_HEADER_TYPE_MFD 0x80 /* Multi-Function Device (possible) */124 /* 0x35-0x3b are reserved */130 /* Header type 1 (PCI-to-PCI bridges) */134 #define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */[all …]
4 [ 0.000000] Linux version 3.10.73-gc33d1bd (android-[email protected]) (gcc versio…6 [ 0.000000] Machine: LGE MSM8992 BULLHEAD rev-1.0129 [ 0.000000] pcpu-alloc: s38976 r0 d22464 u61440 alloc=15*409630 [ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3 [0] 4 [0] 5 32 …-5 lpm_levels.sleep_disabled=1 msm_poweroff.download_mode=0 buildvariant=user androidboot.bootreas…36 [ 0.000000] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes)37 [ 0.000000] software IO TLB [mem 0x72a00000-0x72b00000] (1MB) mapped at [ffffffc072a00000-ffffff…40 [ 0.000000] vmalloc : 0xffffff8000000000 - 0xffffffbbffff0000 (245759 MB)41 [ 0.000000] vmemmap : 0xffffffbc00000000 - 0xffffffbc02000000 ( 32 MB)42 [ 0.000000] modules : 0xffffffbffc000000 - 0xffffffc000000000 ( 64 MB)[all …]
... d, need_size = %d H5: data_retransfer_thread exiting --------> H5_W4_DATA ACK ...