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/linux-6.14.4/drivers/iommu/arm/arm-smmu/
Dqcom_iommu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * IOMMU API for QCOM secure IOMMUs. Somewhat based on arm-smmu.c
13 #include <linux/dma-mapping.h>
17 #include <linux/io-64-nonatomic-hi-lo.h>
18 #include <linux/io-pgtable.h>
33 #include "arm-smmu.h"
54 struct qcom_iommu_ctx *ctxs[]; /* indexed by asid */
62 u8 asid; /* asid and ctx bank # are 1:1 */ member
82 static struct qcom_iommu_ctx * to_ctx(struct qcom_iommu_domain *d, unsigned asid) in to_ctx() argument
84 struct qcom_iommu_dev *qcom_iommu = d->iommu; in to_ctx()
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/linux-6.14.4/drivers/accel/habanalabs/common/
Dcontext.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2021 HabanaLabs, Ltd.
15 struct hl_encaps_signals_mgr *mgr = &handle->ctx->sig_mgr; in encaps_handle_do_release()
18 hw_sob_put(handle->hw_sob); in encaps_handle_do_release()
20 spin_lock(&mgr->lock); in encaps_handle_do_release()
21 idr_remove(&mgr->handles, handle->id); in encaps_handle_do_release()
22 spin_unlock(&mgr->lock); in encaps_handle_do_release()
25 hl_ctx_put(handle->ctx); in encaps_handle_do_release()
56 spin_lock_init(&mgr->lock); in hl_encaps_sig_mgr_init()
57 idr_init(&mgr->handles); in hl_encaps_sig_mgr_init()
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Dmemory.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2022 HabanaLabs, Ltd.
15 #include <linux/pci-p2pdma.h>
21 /* use small pages for supporting non-pow2 (32M/40M/48M) DRAM phys page sizes */
31 struct asic_fixed_properties *prop = &hdev->asic_prop; in set_alloc_page_size()
38 if (prop->supports_user_set_page_size && args->alloc.page_size) { in set_alloc_page_size()
39 psize = args->alloc.page_size; in set_alloc_page_size()
42 dev_err(hdev->dev, "user page size (%#llx) is not power of 2\n", psize); in set_alloc_page_size()
43 return -EINVAL; in set_alloc_page_size()
46 psize = prop->device_mem_alloc_default_page_size; in set_alloc_page_size()
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Ddebugfs.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2021 HabanaLabs, Ltd.
28 return -EBUSY; in hl_debugfs_i2c_read()
31 dev_err(hdev->dev, "I2C transaction length %u, exceeds maximum of %u\n", in hl_debugfs_i2c_read()
33 return -EINVAL; in hl_debugfs_i2c_read()
45 rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), 0, val); in hl_debugfs_i2c_read()
46 if (rc && rc != -EAGAIN) in hl_debugfs_i2c_read()
47 dev_err(hdev->dev, "Failed to read from I2C, error %d\n", rc); in hl_debugfs_i2c_read()
59 return -EBUSY; in hl_debugfs_i2c_write()
62 dev_err(hdev->dev, "I2C transaction length %u, exceeds maximum of %u\n", in hl_debugfs_i2c_write()
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Dcommand_submission.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2021 HabanaLabs, Ltd.
23 * enum hl_cs_wait_status - cs wait status
53 static int _hl_cs_wait_ioctl(struct hl_device *hdev, struct hl_ctx *ctx, u64 timeout_us, u64 seq,
66 * push outcome - store a recent CS outcome in the store in hl_push_cs_outcome()
67 * pop outcome - retrieve a SPECIFIC (by seq) CS outcome from the store in hl_push_cs_outcome()
69 * It has a pre-allocated amount of nodes, each node stores in hl_push_cs_outcome()
84 spin_lock_irqsave(&outcome_store->db_lock, flags); in hl_push_cs_outcome()
86 if (list_empty(&outcome_store->free_list)) { in hl_push_cs_outcome()
87 node = list_last_entry(&outcome_store->used_list, in hl_push_cs_outcome()
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Dhabanalabs.h1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright 2016-2023 HabanaLabs, Ltd.
19 #include <linux/dma-direction.h>
28 #include <linux/io-64-nonatomic-lo-hi.h>
30 #include <linux/dma-buf.h>
45 * bits[63:59] - Encode mmap type
46 * bits[45:0] - mmap offset value
51 #define HL_MMAP_TYPE_SHIFT (59 - PAGE_SHIFT)
110 * enum hl_mmu_page_table_location - mmu page table location
111 * @MMU_DR_PGT: page-table is located on device DRAM.
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Dcommand_buffer.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2019 HabanaLabs, Ltd.
17 static int cb_map_mem(struct hl_ctx *ctx, struct hl_cb *cb) in cb_map_mem() argument
19 struct hl_device *hdev = ctx->hdev; in cb_map_mem()
20 struct asic_fixed_properties *prop = &hdev->asic_prop; in cb_map_mem()
21 u32 page_size = prop->pmmu.page_size; in cb_map_mem()
24 if (!hdev->supports_cb_mapping) { in cb_map_mem()
25 dev_err_ratelimited(hdev->dev, in cb_map_mem()
27 return -EINVAL; in cb_map_mem()
30 if (cb->is_mmu_mapped) in cb_map_mem()
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/linux-6.14.4/arch/mips/mm/
Dcontext.c1 // SPDX-License-Identifier: GPL-2.0
24 u64 asid; in get_new_mmu_context() local
34 asid = asid_cache(cpu); in get_new_mmu_context()
36 if (!((asid += cpu_asid_inc()) & cpu_asid_mask(&cpu_data[cpu]))) { in get_new_mmu_context()
39 local_flush_tlb_all(); /* start new asid cycle */ in get_new_mmu_context()
42 set_cpu_context(cpu, mm, asid); in get_new_mmu_context()
43 asid_cache(cpu) = asid; in get_new_mmu_context()
58 /* Check if our ASID is of an older version and thus invalid */ in check_mmu_context()
94 * context-switch in flush_context()
146 * We had a valid MMID in a previous life, so try to re-use in get_new_mmid()
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/linux-6.14.4/drivers/vhost/
Dvdpa.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018-2020 Intel Corporation.
71 u64 last, u32 asid);
77 return as->id; in iotlb_to_asid()
80 static struct vhost_vdpa_as *asid_to_as(struct vhost_vdpa *v, u32 asid) in asid_to_as() argument
82 struct hlist_head *head = &v->as[asid % VHOST_VDPA_IOTLB_BUCKETS]; in asid_to_as()
86 if (as->id == asid) in asid_to_as()
92 static struct vhost_iotlb *asid_to_iotlb(struct vhost_vdpa *v, u32 asid) in asid_to_iotlb() argument
94 struct vhost_vdpa_as *as = asid_to_as(v, asid); in asid_to_iotlb()
99 return &as->iotlb; in asid_to_iotlb()
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Dvhost.c1 // SPDX-License-Identifier: GPL-2.0-only
49 #define vhost_used_event(vq) ((__virtio16 __user *)&vq->avail->ring[vq->num])
50 #define vhost_avail_event(vq) ((__virtio16 __user *)&vq->used->ring[vq->num])
55 vq->user_be = !virtio_legacy_is_little_endian(); in vhost_disable_cross_endian()
60 vq->user_be = true; in vhost_enable_cross_endian_big()
65 vq->user_be = false; in vhost_enable_cross_endian_little()
72 if (vq->private_data) in vhost_set_vring_endian()
73 return -EBUSY; in vhost_set_vring_endian()
76 return -EFAULT; in vhost_set_vring_endian()
80 return -EINVAL; in vhost_set_vring_endian()
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Dvhost.h1 /* SPDX-License-Identifier: GPL-2.0 */
76 struct eventfd_ctx *ctx; member
147 /* Ring endianness requested by userspace for cross-endian support. */
179 int (*msg_handler)(struct vhost_dev *dev, u32 asid,
187 int (*msg_handler)(struct vhost_dev *dev, u32 asid,
252 if ((vq)->error_ctx) \
253 eventfd_signal((vq)->error_ctx);\
266 * vhost_vq_set_backend - Set backend.
271 * Context: Need to call with vq->mutex acquired.
276 vq->private_data = private_data; in vhost_vq_set_backend()
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/linux-6.14.4/drivers/accel/habanalabs/common/mmu/
Dmmu.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2022 HabanaLabs, Ltd.
16 * hl_mmu_get_funcs() - get MMU functions structure
26 return &hdev->mmu_func[pgt_residency]; in hl_mmu_get_funcs()
31 struct asic_fixed_properties *prop = &hdev->asic_prop; in hl_is_dram_va()
33 return hl_mem_area_inside_range(virt_addr, prop->dmmu.page_size, in hl_is_dram_va()
34 prop->dmmu.start_addr, in hl_is_dram_va()
35 prop->dmmu.end_addr); in hl_is_dram_va()
39 * hl_mmu_init() - initialize the MMU module.
42 * Return: 0 for success, non-zero for failure.
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Dmmu_v1.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2019 HabanaLabs, Ltd.
15 static inline u64 get_hop_pte_addr(struct hl_ctx *ctx, struct hl_mmu_properties *mmu_prop, in get_hop_pte_addr() argument
20 mask = mmu_prop->hop_masks[hop_idx]; in get_hop_pte_addr()
21 shift = mmu_prop->hop_shifts[hop_idx]; in get_hop_pte_addr()
23 ctx->hdev->asic_prop.mmu_pte_size * ((virt_addr & mask) >> shift); in get_hop_pte_addr()
26 static int dram_default_mapping_init(struct hl_ctx *ctx) in dram_default_mapping_init() argument
28 struct hl_device *hdev = ctx->hdev; in dram_default_mapping_init()
29 struct asic_fixed_properties *prop = &hdev->asic_prop; in dram_default_mapping_init()
34 if ((!prop->dram_supports_virtual_memory) || in dram_default_mapping_init()
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Dmmu_v2_hr.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2020-2022 HabanaLabs, Ltd.
13 static struct pgt_info *hl_mmu_v2_hr_get_pgt_info(struct hl_ctx *ctx, u64 phys_hop_addr) in hl_mmu_v2_hr_get_pgt_info() argument
17 hash_for_each_possible(ctx->hr_mmu_phys_hash, pgt_info, node, in hl_mmu_v2_hr_get_pgt_info()
19 if (phys_hop_addr == pgt_info->phys_addr) in hl_mmu_v2_hr_get_pgt_info()
25 static void hl_mmu_v2_hr_add_pgt_info(struct hl_ctx *ctx, struct pgt_info *pgt_info, in hl_mmu_v2_hr_add_pgt_info() argument
28 hash_add(ctx->hr_mmu_phys_hash, &pgt_info->node, phys_addr); in hl_mmu_v2_hr_add_pgt_info()
31 static struct pgt_info *hl_mmu_v2_hr_get_hop0_pgt_info(struct hl_ctx *ctx) in hl_mmu_v2_hr_get_hop0_pgt_info() argument
33 return &ctx->hdev->mmu_priv.hr.mmu_asid_hop0[ctx->asid]; in hl_mmu_v2_hr_get_hop0_pgt_info()
37 * hl_mmu_v2_hr_init() - initialize the MMU module.
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Dmmu_v2.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2020 HabanaLabs, Ltd.
15 * hl_mmu_v2_ctx_init() - initialize a context for using the MMU module.
16 * @ctx: pointer to the context structure to initialize.
20 * Return: 0 on success, non-zero otherwise.
22 static int hl_mmu_v2_ctx_init(struct hl_ctx *ctx) in hl_mmu_v2_ctx_init() argument
24 hash_init(ctx->mmu_shadow_hash); in hl_mmu_v2_ctx_init()
30 * hl_mmu_v2_ctx_fini - disable a ctx from using the mmu module
32 * @ctx: pointer to the context structure
35 * - Free any pgts which were not freed yet
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/linux-6.14.4/arch/mips/include/asm/
Dmmu_context.h26 #include <asm-generic/mm_hooks.h>
80 * allow the kernel to create wired entries with the MMID of current->active_mm
92 * as a software asid extension.
98 return ~(u64)(asid_mask | (asid_mask - 1)); in asid_version_mask()
109 return atomic64_read(&mm->context.mmid); in cpu_context()
111 return mm->context.asid[cpu]; in cpu_context()
115 struct mm_struct *mm, u64 ctx) in set_cpu_context() argument
118 atomic64_set(&mm->context.mmid, ctx); in set_cpu_context()
120 mm->context.asid[cpu] = ctx; in set_cpu_context()
148 mm->context.bd_emupage_allocmap = NULL; in init_new_context()
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/linux-6.14.4/arch/m68k/include/asm/
Dmmu_context.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <asm-generic/mm_hooks.h>
30 mm_context_t ctx; in get_mmu_context() local
32 if (mm->context != NO_CONTEXT) in get_mmu_context()
38 ctx = next_mmu_context; in get_mmu_context()
39 while (test_and_set_bit(ctx, context_map)) { in get_mmu_context()
40 ctx = find_next_zero_bit(context_map, LAST_CONTEXT+1, ctx); in get_mmu_context()
41 if (ctx > LAST_CONTEXT) in get_mmu_context()
42 ctx = 0; in get_mmu_context()
44 next_mmu_context = (ctx + 1) & LAST_CONTEXT; in get_mmu_context()
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/linux-6.14.4/drivers/accel/habanalabs/gaudi/
Dgaudi.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2022 HabanaLabs, Ltd.
27 * - Range registers
28 * - MMU
31 * - Range registers (protect the first 512MB)
34 * - Range registers
35 * - Protection bits
40 * - DMA is not secured.
41 * - PQ and CQ are secured.
42 * - CP is secured: The driver needs to parse CB but WREG should be allowed
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/linux-6.14.4/Documentation/devicetree/bindings/iommu/
Dqcom,iommu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Konrad Dybcio <[email protected]>
13 Qualcomm "B" family devices which are not compatible with arm-smmu have
16 to non-secure vs secure interrupt line.
21 - items:
22 - enum:
23 - qcom,msm8916-iommu
24 - qcom,msm8917-iommu
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/linux-6.14.4/drivers/misc/sgi-gru/
Dgrumain.c1 // SPDX-License-Identifier: GPL-2.0-or-later
52 /*--------- ASID Management -------------------------------------------
58 * asid in use ("x"s below). Set "limit" to this value.
66 * Each time MAX_ASID is reached, increment the asid generation. Since
67 * the search for in-use asids only checks contexts with GRUs currently
69 * a context, the asid generation of the GTS asid is rechecked. If it
70 * doesn't match the current generation, a new asid will be assigned.
72 * 0---------------x------------x---------------------x----|
73 * ^-next ^-limit ^-MAX_ASID
75 * All asid manipulation & context loading/unloading is protected by the
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Dgrutables.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
28 * +-----------------+
37 * +-----------------+
39 * +-----------------+ _______ +-------------+
45 * |/////////////////| / |-------------|
47 * +-----------------+ | |
49 * +-----------------+ | |
51 * +-----------------+ \____________ +-------------+
53 * +-----------------+
55 * +-----------------+
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/linux-6.14.4/drivers/accel/habanalabs/gaudi2/
Dgaudi2.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2020-2022 HabanaLabs, Ltd.
45 * since the code already has built-in support for binning of up to MAX_FAULTY_TPCS TPCs
126 #define GAUDI2_PMMU_SPI_SEI_ENABLE_MASK GENMASK(GAUDI2_NUM_OF_MMU_SPI_SEI_CAUSE - 2, 0)
127 #define GAUDI2_HMMU_SPI_SEI_ENABLE_MASK GENMASK(GAUDI2_NUM_OF_MMU_SPI_SEI_CAUSE - 1, 0)
131 #define GAUDI2_VDEC_MSIX_ENTRIES (GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM - \
134 #define ENGINE_ID_DCORE_OFFSET (GAUDI2_DCORE1_ENGINE_ID_EDMA_0 - GAUDI2_DCORE0_ENGINE_ID_EDMA_0)
164 /* HW scrambles only bits 0-25 */
2114 * and read global errors. Most HW blocks are addressable and those who aren't (N/A)-
2137 {HBM_MC_SPI_THR_ENG_MASK, "temperature-based throttling engaged"},
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/linux-6.14.4/arch/arm64/boot/dts/qcom/
Dmsm8976.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016-2022, AngeloGioacchino Del Regno
9 #include <dt-bindings/clock/qcom,gcc-msm8976.h>
10 #include <dt-bindings/clock/qcom,rpmcc.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
17 interrupt-parent = <&intc>;
18 #address-cells = <2>;
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/linux-6.14.4/drivers/vdpa/mlx5/net/
Dmlx5_vnet.c1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
47 #define MLX5_FEATURE(_mvdev, _feature) (!!((_mvdev)->actual_features & BIT_ULL(_feature)))
149 if (!(mvdev->actual_features & BIT_ULL(VIRTIO_NET_F_MQ))) { in is_index_valid()
150 if (!(mvdev->actual_features & BIT_ULL(VIRTIO_NET_F_CTRL_VQ))) in is_index_valid()
156 return idx <= mvdev->max_idx; in is_index_valid()
179 /* TODO: cross-endian support */
183 (mvdev->actual_features & BIT_ULL(VIRTIO_F_VERSION_1)); in mlx5_vdpa_is_little_endian()
198 if (!(mvdev->actual_features & BIT_ULL(VIRTIO_NET_F_MQ))) in ctrl_vq_idx()
201 return mvdev->max_vqs; in ctrl_vq_idx()
283 struct mlx5_vdpa_dev *mvdev = &ndev->mvdev; in create_tis()
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/linux-6.14.4/arch/x86/include/asm/
Dsev.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 #include <linux/sev-guest.h>
15 #include <asm/sev-common.h>
73 u64 mask = (1ULL << bits) - 1; in lower_bits()
110 u32 asid; member
177 u8 payload[PAGE_SIZE - sizeof(struct snp_guest_msg_hdr)];
212 * The secrets page contains 96-bytes of reserved field that can be used by
263 * Avoid information leakage by double-buffering shared messages
270 struct aesgcm_ctx *ctx; member
285 u8 svsm_buffer[PAGE_SIZE - 8];
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