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/linux-6.14.4/Documentation/arch/loongarch/
Dirq-chip-model.rst8 with LS7A chipsets. The irq chips in LoongArch computers include CPUINTC (CPU Core
14 CPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are per-package
23 to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
25 to LIOINTC, and then CPUINTC::
28 | IPI | --> | CPUINTC | <-- | Timer |
60 to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
62 to CPUINTC directly::
65 | IPI | --> | CPUINTC | <-- | Timer |
92 go to CPUINTC directly, CPU UARTS interrupts go to PCH-PIC, while all other
94 Extended I/O Interrupt Controller), and then go to CPUINTC directly::
[all …]
/linux-6.14.4/arch/mips/boot/dts/realtek/
Drtl83xx.dtsi12 cpuintc: cpuintc { label
31 interrupt-parent = <&cpuintc>;
48 interrupt-parent = <&cpuintc>;
/linux-6.14.4/arch/mips/boot/dts/ralink/
Dmt7620a.dtsi13 cpuintc: cpuintc { label
40 interrupt-parent = <&cpuintc>;
Drt2880.dtsi13 cpuintc: cpuintc { label
40 interrupt-parent = <&cpuintc>;
Drt3883.dtsi13 cpuintc: cpuintc { label
40 interrupt-parent = <&cpuintc>;
Drt3050.dtsi13 cpuintc: cpuintc { label
40 interrupt-parent = <&cpuintc>;
Dmt7628a.dtsi24 cpuintc: interrupt-controller { label
160 interrupt-parent = <&cpuintc>;
293 interrupt-parent = <&cpuintc>;
/linux-6.14.4/Documentation/translations/zh_CN/arch/loongarch/
Dirq-chip-model.rst31 | IPI | --> | CPUINTC | <-- | Timer |
67 | IPI | --> | CPUINTC | <-- | Timer |
98 | IPI |--> | CPUINTC(0-255vcpu)| <-- | Timer |
154 | IPI | --> | CPUINTC | <-- | Timer |
180 CPUINTC::
238 - CPUINTC:即《龙芯架构参考手册卷一》第7.4节所描述的CSR.ECFG/CSR.ESTAT寄存器及其
/linux-6.14.4/Documentation/translations/zh_TW/arch/loongarch/
Dirq-chip-model.rst31 | IPI | --> | CPUINTC | <-- | Timer |
67 | IPI | --> | CPUINTC | <-- | Timer |
93 CPUINTC::
151 - CPUINTC:即《龍芯架構參考手冊卷一》第7.4節所描述的CSR.ECFG/CSR.ESTAT寄存器及其
/linux-6.14.4/Documentation/devicetree/bindings/interrupt-controller/
Dgoogle,goldfish-pic.txt14 cpuintc {
28 interrupt-parent = <&cpuintc>;
Dqca,ath79-misc-intc.txt27 interrupt-parent = <&cpuintc>;
40 interrupt-parent = <&cpuintc>;
/linux-6.14.4/arch/mips/boot/dts/qca/
Dar9132.dtsi22 cpuintc: interrupt-controller { label
40 interrupt-parent = <&cpuintc>;
116 interrupt-parent = <&cpuintc>;
Dar9331.dtsi22 cpuintc: interrupt-controller { label
44 interrupt-parent = <&cpuintc>;
104 interrupt-parent = <&cpuintc>;
/linux-6.14.4/arch/mips/boot/dts/loongson/
Dloongson64g-package.dtsi9 cpuintc: interrupt-controller { label
31 interrupt-parent = <&cpuintc>;
Dloongson64c-package.dtsi9 cpuintc: interrupt-controller { label
34 interrupt-parent = <&cpuintc>;
Dloongson64v_4core_virtio.dts11 cpuintc: interrupt-controller { label
33 interrupt-parent = <&cpuintc>;
Dloongson64-2k1000.dtsi32 cpuintc: interrupt-controller { label
69 interrupt-parent = <&cpuintc>;
89 interrupt-parent = <&cpuintc>;
/linux-6.14.4/arch/loongarch/boot/dts/
Dloongson-2k0500.dtsi34 cpuintc: interrupt-controller { label
135 interrupt-parent = <&cpuintc>;
153 interrupt-parent = <&cpuintc>;
168 interrupt-parent = <&cpuintc>;
/linux-6.14.4/arch/mips/boot/dts/mscc/
Dluton.dtsi25 cpuintc: interrupt-controller { label
64 interrupt-parent = <&cpuintc>;
Dserval.dtsi28 cpuintc: interrupt-controller { label
67 interrupt-parent = <&cpuintc>;
Djaguar2.dtsi29 cpuintc: interrupt-controller { label
68 interrupt-parent = <&cpuintc>;
/linux-6.14.4/arch/mips/boot/dts/xilfpga/
Dnexys4ddr.dts22 cpuintc: interrupt-controller { label
37 interrupt-parent = <&cpuintc>;
/linux-6.14.4/drivers/irqchip/
Dirq-loongarch-cpu.c69 .name = "CPUINTC",
163 cpuintc_handle = irq_domain_alloc_named_fwnode("CPUINTC"); in cpuintc_acpi_init()
/linux-6.14.4/arch/mips/boot/dts/ingenic/
Dx1830.dtsi25 cpuintc: interrupt-controller { label
39 interrupt-parent = <&cpuintc>;
92 interrupt-parent = <&cpuintc>;
Dx1000.dtsi25 cpuintc: interrupt-controller { label
39 interrupt-parent = <&cpuintc>;
99 interrupt-parent = <&cpuintc>;

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