Lines Matching full:cpuintc

8 with LS7A chipsets. The irq chips in LoongArch computers include CPUINTC (CPU Core
14 CPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are per-package
23 to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
25 to LIOINTC, and then CPUINTC::
28      | IPI | --> | CPUINTC | <-- | Timer |
60 to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
62 to CPUINTC directly::
65           | IPI | --> | CPUINTC | <-- | Timer |
92 go to CPUINTC directly, CPU UARTS interrupts go to PCH-PIC, while all other
94 Extended I/O Interrupt Controller), and then go to CPUINTC directly::
97        | IPI |--> | CPUINTC(0-255vcpu)| <-- | Timer |
156 to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, PCH-MSI interrupts go
157 to AVECINTC, and then go to CPUINTC directly, while all other devices interrupts
158 go to PCH-PIC/PCH-LPC and gathered by EIOINTC, and then go to CPUINTC directly::
161  | IPI | --> |        CPUINTC        | <-- | Timer |
187 CPUINTC::
245     - CPUINTC is CSR.ECFG/CSR.ESTAT and its interrupt controller described