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/linux-6.14.4/Documentation/devicetree/bindings/memory-controllers/
Dti,gpmc-child.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc-child.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <[email protected]>
11 - Roger Quadros <[email protected]>
24 gpmc,sync-clk-ps:
28 # Chip-select signal timings corresponding to GPMC_CONFIG2:
29 gpmc,cs-on-ns:
33 gpmc,cs-rd-off-ns:
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Dst,stm32-fmc2-ebi-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christophe Kerello <[email protected]>
11 - Marek Vasut <[email protected]>
14 st,fmc2-ebi-cs-transaction-type:
25 8: Synchronous read synchronous write PSRAM.
26 9: Synchronous read asynchronous write PSRAM.
27 10: Synchronous read synchronous write NOR.
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/linux-6.14.4/include/linux/platform_data/
Dgpmc-omap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2014 Texas Instruments, Inc. - https://www.ti.com
34 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
37 u32 cs_wr_off; /* Write deassertion time */
42 u32 adv_wr_off; /* Write deassertion time */
45 u32 adv_aad_mux_wr_off; /* ADV write deassertion time for AAD */
59 u32 access; /* Start-cycle to first data valid delay */
61 u32 wr_cycle; /* Total write cycle time */
97 u32 t_cez_w; /* write CS deassertion to high Z */
100 u32 t_wpl; /* write assertion time */
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/linux-6.14.4/Documentation/devicetree/bindings/dma/
Drenesas,nbpfaxi.txt1 * Renesas "Type-AXI" NBPFAXI* DMA controllers
7 - compatible: must be one of
17 - #dma-cells: must be 2: the first integer is a terminal number, to which this
26 - max-burst-mem-read: limit burst size for memory reads
28 than using the maximum burst size allowed by the hardware's buffer size.
29 - max-burst-mem-write: limit burst size for memory writes
31 than using the maximum burst size allowed by the hardware's buffer size.
32 If both max-burst-mem-read and max-burst-mem-write are set, DMA_MEM_TO_MEM
35 You can use dma-channels and dma-requests as described in dma.txt, although they
40 dma: dma-controller@48000000 {
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Dintel,ldma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - [email protected]
11 - [email protected]
14 - $ref: dma-controller.yaml#
19 - intel,lgm-cdma
20 - intel,lgm-dma2tx
21 - intel,lgm-dma1rx
22 - intel,lgm-dma1tx
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/linux-6.14.4/drivers/dma/qcom/
Dhidma_mgmt.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
17 #include <linux/dma-mapping.h>
45 "maximum write burst (default: ACPI/DT value)");
50 "maximum read burst (default: ACPI/DT value)");
55 "maximum number of write transactions (default: ACPI/DT value)");
67 if (!is_power_of_2(mgmtdev->max_write_request) || in hidma_mgmt_setup()
68 (mgmtdev->max_write_request < 128) || in hidma_mgmt_setup()
69 (mgmtdev->max_write_request > 1024)) { in hidma_mgmt_setup()
70 dev_err(&mgmtdev->pdev->dev, "invalid write request %d\n", in hidma_mgmt_setup()
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Dqcom_adm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
10 #include <linux/dma-mapping.h>
27 #include "../virt-dma.h"
29 /* ADM registers - calculated from channel number and security domain */
99 #define ADM_MAX_XFER (SZ_64K - 1)
100 #define ADM_MAX_ROWS (SZ_64K - 1)
177 * adm_free_chan - Frees dma resources associated with the specific channel
190 * adm_get_blksize - Get block size from burst value
192 * @burst: Burst size of transaction
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/linux-6.14.4/drivers/misc/
Ddw-xdata-pcie.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/pci-epf.h>
20 #define DW_XDATA_DRIVER_NAME "dw-xdata-pcie"
75 return dw->rg_region.vaddr; in __dw_regs()
80 u32 burst; in dw_xdata_stop() local
82 mutex_lock(&dw->mutex); in dw_xdata_stop()
84 burst = readl(&(__dw_regs(dw)->burst_cnt)); in dw_xdata_stop()
86 if (burst & BURST_REPEAT) { in dw_xdata_stop()
87 burst &= ~(u32)BURST_REPEAT; in dw_xdata_stop()
88 writel(burst, &(__dw_regs(dw)->burst_cnt)); in dw_xdata_stop()
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/linux-6.14.4/arch/arm/boot/dts/ti/omap/
Domap3-gta04a5one.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-18 H. Nikolaus Schaller <[email protected]>
6 #include "omap3-gta04a5.dts"
13 gpmc_pins: gpmc-pins {
14 pinctrl-single,pins = <
45 pinctrl-names = "default";
46 pinctrl-0 = <&gpmc_pins>;
48 /delete-node/ nand@0,0;
52 #address-cells = <1>;
53 #size-cells = <1>;
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Domap3-igep.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 /dts-v1/;
19 stdout-path = &uart3;
23 compatible = "ti,omap-twl4030";
28 vdd33: regulator-vdd33 {
29 compatible = "regulator-fixed";
30 regulator-name = "vdd33";
31 regulator-always-on;
37 gpmc_pins: gpmc-pins {
38 pinctrl-single,pins = <
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/linux-6.14.4/drivers/dma/dw-edma/
Ddw-edma-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
17 #include <linux/dma-mapping.h>
19 #include "dw-edma-core.h"
20 #include "dw-edma-v0-core.h"
21 #include "dw-hdma-v0-core.h"
23 #include "../virt-dma.h"
28 return &dchan->dev->device; in dchan2dev()
34 return &chan->vc.chan.dev->device; in chan2dev()
46 struct dw_edma_chip *chip = chan->dw->chip; in dw_edma_get_pci_address()
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/linux-6.14.4/drivers/char/tpm/
Dtpm_tis_i2c_cr50.c1 // SPDX-License-Identifier: GPL-2.0
10 * - Use an interrupt for transaction status instead of hardcoded delays.
11 * - Must use write+wait+read read protocol.
12 * - All 4 bytes of status register must be read/written at once.
13 * - Burst count max is 63 bytes, and burst count behaves slightly differently
15 * - When reading from FIFO the full burstcnt must be read instead of just
48 * struct tpm_i2c_cr50_priv_data - Driver private data.
63 * tpm_cr50_i2c_int_handler() - cr50 interrupt handler.
77 struct tpm_i2c_cr50_priv_data *priv = dev_get_drvdata(&chip->dev); in tpm_cr50_i2c_int_handler()
79 complete(&priv->tpm_ready); in tpm_cr50_i2c_int_handler()
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/linux-6.14.4/include/linux/iio/imu/
Dadis.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Author: Lars-Peter Clausen <[email protected]>
28 * struct adis_timeouts - ADIS chip variant timeouts
29 * @reset_ms - Wait time after rst pin goes inactive
30 * @sw_reset_ms - Wait time after sw reset command
31 * @self_test_ms - Wait time after self test command
40 * struct adis_data - ADIS chip variant specific data
42 * @write_delay: SPI delay for write operations in us
49 * @self_test_mask: Bitmask of supported self-test operations
51 * @self_test_no_autoclear: True if device's self-test needs clear of ctrl reg
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/linux-6.14.4/drivers/media/pci/tw5864/
Dtw5864-reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * TW5864 driver - registers description
8 /* According to TW5864_datasheet_0.6d.pdf, tw5864b1-ds.pdf */
10 /* Register Description - Direct Map Space */
11 /* 0x0000 ~ 0x1ffc - H264 Register Map */
23 /* Enable bit for Host Burst Access */
76 * 0->3 4 VLC data buffer in DDR (1M each)
77 * 0->7 8 VLC data buffer in DDR (512k each)
147 /* DDR-DPR Burst Read Enable */
157 * 0 Single R/W Access (Host <-> DDR)
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/linux-6.14.4/include/linux/mtd/
Dhyperbus.h1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
18 #define HYPERBUS_BT 0x20 /* Burst Type */
28 * struct hyperbus_device - struct representing HyperBus slave device
47 * struct hyperbus_ops - struct representing custom HyperBus operations
48 * @read16: read 16 bit of data from flash in a single burst. Used to read
50 * @write16: write 16 bit of data to flash in a single burst. Used to
51 * send cmd to flash or write single 16 bit word at a time.
69 * struct hyperbus_ctlr - struct representing HyperBus controller
82 * hyperbus_register_device - probe and register a HyperBus slave memory device
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/linux-6.14.4/Documentation/devicetree/bindings/net/
Dsnps,dwc-qos-ethernet.txt13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
18 - "snps,dwc-qos-ethernet-4.10"
20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
22 - reg: Address and length of the register set for the device
23 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
24 same order. See ../clock/clock-bindings.txt.
25 - clock-names: May contain any/all of the following depending on the IP
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Dsnps,dwmac.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Torgue <[email protected]>
11 - Giuseppe Cavallaro <[email protected]>
12 - Jose Abreu <[email protected]>
23 - snps,dwmac
24 - snps,dwmac-3.40a
25 - snps,dwmac-3.50a
26 - snps,dwmac-3.610
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/linux-6.14.4/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/
Ddma_public.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 /*! Write to a control register of DMA[ID]
37 /*! Set maximum burst size of DMA[ID]
40 \param conn[in] Connection to set max burst size for
41 \param max_burst_size[in] Maximum burst size in words
/linux-6.14.4/drivers/net/ethernet/stmicro/stmmac/
Ddwmac1000.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 Copyright (C) 2007-2009 STMicroelectronics Ltd
23 #define GMAC_WAKEUP_FILTER 0x00000028 /* Wake-up Frame Filter */
79 #define GMAC_ADDR_HIGH(reg) ((reg > 15) ? 0x00000800 + (reg - 16) * 8 : \
81 #define GMAC_ADDR_LOW(reg) ((reg > 15) ? 0x00000804 + (reg - 16) * 8 : \
108 #define GMAC_CONTROL_BE 0x00200000 /* Frame Burst Enable */
119 #define GMAC_CONTROL_LM 0x00001000 /* Loop-back mode */
145 #define GMAC_MII_ADDR_WRITE 0x00000002 /* MII Write */
159 #define GMAC_DEBUG_TWCSTS BIT(22) /* MTL Tx FIFO Write Controller */
177 #define GMAC_DEBUG_RXFSTS_MASK GENMASK(9, 8) /* MTL Rx FIFO Fill-level */
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/linux-6.14.4/arch/sparc/include/asm/
Ddma.h1 /* SPDX-License-Identifier: GPL-2.0 */
42 #define DMA_ST_WRITE 0x00000100 /* write from device to memory */
50 #define DMA_SCSI_SBUS64 0x00008000 /* HME: Enable 64-bit SBUS mode. */
55 #define DMA_E_BURSTS 0x000c0000 /* ENET: SBUS r/w burst mask */
56 #define DMA_E_BURST32 0x00040000 /* ENET: SBUS 32 byte r/w burst */
57 #define DMA_E_BURST16 0x00000000 /* ENET: SBUS 16 byte r/w burst */
58 #define DMA_BRST_SZ 0x000c0000 /* SCSI: SBUS r/w burst size */
62 #define DMA_BRST0 0x00080000 /* SCSI: no bursts (non-HME gate arrays) */
66 #define DMA_EN_ENETAUI DMA_3CLKS /* Put lance into AUI-cable mode */
75 /* Values describing the burst-size property from the PROM */
/linux-6.14.4/drivers/ata/
Dahci_sunxi.c1 // SPDX-License-Identifier: GPL-2.0-only
22 #define DRV_NAME "ahci-sunxi"
118 if (--timeout == 0) { in ahci_sunxi_phy_init()
120 return -EIO; in ahci_sunxi_phy_init()
133 if (--timeout == 0) { in ahci_sunxi_phy_init()
135 return -EIO; in ahci_sunxi_phy_init()
150 struct ahci_host_priv *hpriv = ap->host->private_data; in ahci_sunxi_start_engine()
156 * User's Guide document (TMS320C674x/OMAP-L1x Processor in ahci_sunxi_start_engine()
173 * transmit (system bus read, device write) operation. [...] in ahci_sunxi_start_engine()
177 * for receive (system bus write, device read) operation. [...] in ahci_sunxi_start_engine()
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/linux-6.14.4/drivers/net/ethernet/altera/
Daltera_msgdmahw.h1 /* SPDX-License-Identifier: GPL-2.0-only */
17 u32 burst_seq_num; /* bit 31:24 write burst
18 * bit 23:16 read burst
21 u32 stride; /* bit 31:16 write stride
79 u32 control; /* Read/Write */
80 u32 rw_fill_level; /* bit 31:16 - write fill level
81 * bit 15:0 - read fill level
84 u32 rw_seq_num; /* bit 31:16 - write sequence number
85 * bit 15:0 - read sequence number
/linux-6.14.4/Documentation/userspace-api/media/dvb/
Dfe-diseqc-send-burst.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
13 FE_DISEQC_SEND_BURST - Sends a 22KHz tone burst for 2x1 mini DiSEqC satellite selection.
34 This ioctl is used to set the generation of a 22kHz tone burst for mini
36 read/write permissions.
39 `Digital Satellite Equipment Control (DiSEqC) - Simple "ToneBurst" Detection Circuit specification.…
46 On error -1 is returned, and the ``errno`` variable is set
50 :ref:`Generic Error Codes <gen-errors>` chapter.
/linux-6.14.4/drivers/rtc/
Drtc-max6900.c1 // SPDX-License-Identifier: GPL-2.0-only
21 #define MAX6900_REG_SC 0 /* seconds 00-59 */
22 #define MAX6900_REG_MN 1 /* minutes 00-59 */
23 #define MAX6900_REG_HR 2 /* hours 00-23 */
24 #define MAX6900_REG_DT 3 /* day of month 00-31 */
25 #define MAX6900_REG_MO 4 /* month 01-12 */
26 #define MAX6900_REG_DW 5 /* day of week 1-7 */
27 #define MAX6900_REG_YR 6 /* year 00-99 */
33 #define MAX6900_BURST_LEN 8 /* can burst r/w first 8 regs */
35 #define MAX6900_REG_CT_WP (1 << 7) /* Write Protect */
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/linux-6.14.4/drivers/media/dvb-frontends/
Dcx24116.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 Conexant cx24116/cx24118 - DVBS/S2 Satellite demod/tuner driver
5 Copyright (C) 2006-2008 Steven Toth <[email protected]>
6 Copyright (C) 2006-2007 Georg Acher
7 Copyright (C) 2007-2008 Darron Broad
45 #define CX24116_DEFAULT_FIRMWARE "dvb-fe-cx24116.fw"
74 /* Select DVB-S demodulator, else DVB-S2 */
115 /* DiSEqC burst */
119 /* DiSEqC tone burst */
128 MODULE_PARM_DESC(esno_snr, "SNR return units, 0=PERCENTAGE 0-100, "\
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