Lines Matching +full:burst +full:- +full:write

1 // SPDX-License-Identifier: GPL-2.0-only
22 #define DRV_NAME "ahci-sunxi"
118 		if (--timeout == 0) {  in ahci_sunxi_phy_init()
120 			return -EIO;  in ahci_sunxi_phy_init()
133 		if (--timeout == 0) {  in ahci_sunxi_phy_init()
135 			return -EIO;  in ahci_sunxi_phy_init()
150 	struct ahci_host_priv *hpriv = ap->host->private_data;  in ahci_sunxi_start_engine()
156 	 *   User's Guide document (TMS320C674x/OMAP-L1x Processor  in ahci_sunxi_start_engine()
173 	 *     transmit (system bus read, device write) operation. [...]  in ahci_sunxi_start_engine()
177 	 *     for receive (system bus write, device read) operation. [...]  in ahci_sunxi_start_engine()
179 	 *   TXABL: Transmit Burst Limit.  in ahci_sunxi_start_engine()
181 	 *     burst size. [...]  in ahci_sunxi_start_engine()
183 	 *   RXABL: Receive Burst Limit.  in ahci_sunxi_start_engine()
184 	 *     Allows software to limit the VBUSP master write burst  in ahci_sunxi_start_engine()
193 	 *     sunxi_clrsetbits(hpriv->mmio + AHCI_P0DMACR, 0x0000ffff,  in ahci_sunxi_start_engine()
196 	sunxi_clrsetbits(hpriv->mmio + AHCI_P0DMACR, 0x0000ffff, 0x00004433);  in ahci_sunxi_start_engine()
215 	struct device *dev = &pdev->dev;  in ahci_sunxi_probe()
223 	hpriv->start_engine = ahci_sunxi_start_engine;  in ahci_sunxi_probe()
229 	rc = ahci_sunxi_phy_init(dev, hpriv->mmio);  in ahci_sunxi_probe()
233 	hpriv->flags = AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_MSI |  in ahci_sunxi_probe()
242 		hpriv->flags |= AHCI_HFLAG_NO_PMP;  in ahci_sunxi_probe()
260 	struct ahci_host_priv *hpriv = host->private_data;  in ahci_sunxi_resume()
267 	rc = ahci_sunxi_phy_init(dev, hpriv->mmio);  in ahci_sunxi_resume()
287 	{ .compatible = "allwinner,sun4i-a10-ahci", },
288 	{ .compatible = "allwinner,sun8i-r40-ahci", },