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/aosp_15_r20/external/mesa3d/src/freedreno/afuc/
H A Dmeson.build28 input: ['afuc.xml'],
36 'afuc-asm',
64 test('afuc-asm',
70 test('afuc-asm-a7xx',
79 'afuc-isa',
80 input: ['afuc.xml'],
81 output: ['afuc-isa.c', 'afuc-isa.h'],
91 'afuc-disasm',
130 test('afuc-disasm',
136 test('afuc-disasm-a7xx',
H A DREADME.rst34 "Adreno Five MicroCode" or "afuc". (No idea what Qualcomm calls
53 The afuc instruction set is heavily inspired by MIPS, but not exactly
74 used to :ref:`afuc-read<read>` from various queues and
75 :ref:`afuc-reg-writes<write GPU registers>`. In addition there is a ``$rem``
130 See explanation in :ref:`afuc-branch`
154 The :ref:`cmp <afuc-alu-cmp>` instruction can be paired with the
189 In afuc this only requires a delay slot for the second branch::
217 Afuc has a special NOP encoding where the low 24 bits are ignored by the
360 often used with :ref:`afuc-mem-writes <NRT_DATA>`.
457 :ref:`afuc-pipe-regs <pipe registers>` and they can only be used for writes but
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H A Ddisasm.c24 #include "afuc.h"
25 #include "afuc-isa.h"
H A Demu.c19 #include "afuc-isa.h"
32 * AFUC emulator. Currently only supports a6xx
H A Disa.h13 #include "afuc.h"
H A Dutil.h12 * AFUC disasm / asm helpers
H A Dasm.h11 #include "afuc.h"
H A Dasm.c20 #include "afuc.h"
H A Demu.h14 #include "afuc.h"
H A Dutil.c14 #include "afuc.h"
H A Dafuc.xml30 Encoding of an afuc instruction. All instructions are 32b.
/aosp_15_r20/external/mesa3d/src/freedreno/.gitlab-ci/traces/
H A Dafuc_test.asm24 ; the afuc assembler/disassembler. Note, it won't actually work if you try to
124 ; Euclid's algorithm in afuc: https://en.wikipedia.org/wiki/Euclidean_algorithm
125 ; Since afuc doesn't do modulo, we implement the subtraction-based version.
H A Dafuc_test_a7xx.asm24 ; the afuc assembler/disassembler. This is the a7xx variant, for testing new
153 ; Euclid's algorithm in afuc: https://en.wikipedia.org/wiki/Euclidean_algorithm
154 ; Since afuc doesn't do modulo, we implement the subtraction-based version.
/aosp_15_r20/external/mesa3d/src/freedreno/registers/adreno/
H A Dadreno_control_regs.xml9 the afuc instruction set was introduced.
40 <doc> Controls high 32 bits used by store afuc instruction </doc>
153 <doc> Controls high 32 bits used by load and store afuc instructions </doc>
330 <doc> Controls high 32 bits used by load and store afuc instructions </doc>
/aosp_15_r20/external/mesa3d/docs/drivers/
H A Dfreedreno.rst57 and writes to the hardware registers. See `afuc
58 <https://gitlab.freedesktop.org/mesa/mesa/-/blob/main/src/freedreno/afuc/README.rst>`__.
351 afuc-disasm -v a650_sqe.fw > a650_sqe.fw.disasm
/aosp_15_r20/external/mesa3d/docs/relnotes/
H A D24.1.0.rst1355 - freedreno/afuc: Decode (peek) modifier
1356 - freedreno/afuc: Add missing ALU encode case for bic
1357 - freedreno/afuc: Bump max instructions for a7xx
1358 - freedreno/afuc: Fix setbit/clrbit parsing
1359 - freedreno/afuc: Use left recursion in parser
1360 - freedreno/afuc: Improve jump table handling
1361 - freedreno/afuc: Add .align directive
1362 - freedreno/afuc: Add more general T_IDENTIFIER in lexer
1363 - freedreno/afuc: Add support for multiple sections when assembling
1364 - freedreno/afuc: Allow -e option on a7xx
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H A D21.2.0.rst3618 - freedreno/afuc: Print uintptr_t with PRIxPTR
4491 - freedreno/afuc: Re-indent
4561 - freedreno/afuc: Split out instruction decode helper
4562 - freedreno/afuc: Split out utils
4563 - freedreno/afuc: Clean up special regs
4564 - freedreno/afuc: Add pipe reg name decoding
4565 - freedreno/afuc: Add emulator mode to afuc-disasm
4567 - freedreno/afuc: Extract full gpu-id
4568 - freedreno/afuc: Split out helpers to parse labels and packet-table
4569 - freedreno/afuc: Add emulator support to run bootstrap
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H A D21.3.4.rst84 - freedreno/afuc: Disable the disassembler on 32-bit builds.
H A D24.0.0.rst113 - mesa:freedreno / afuc-disasm unit test failure
839 - freedreno/afuc: Handle store instruction on a5xx
840 - freedreno/afuc: Add separate "SQE registers"
841 - freedreno/afuc: Use SQE registers for call stack
842 - freedreno/afuc: Add syntax for pre-increment addressing
843 - freedreno/afuc: Decode (sdsN) modifier
845 - freedreno/afuc: README updates for a7xx
846 - freedreno/afuc: Fix gen autodetection for a7xx
H A D20.3.0.rst1112 - freedreno/afuc: Fix printing preemptleave on a5xx
1113 - freedreno/afuc: Handle setsecure opcode
1114 - freedreno/afuc: Add iret
1115 - freedreno/afuc: Handle xmov modifiers
1116 - freedreno/afuc: Make 0 a valid number
1117 - freedreno/afuc: Install asm/disasm
1118 - freedreno: Add afuc regression test
H A D23.3.0.rst1146 - afuc: Rework and significantly expand README.rst
1159 - afuc: Fix xmov lexer typo
1160 - afuc: Convert to isaspec
1161 - afuc: Add setbit/clrbit
1162 - afuc: Fix writing $00
1163 - freedreno/afuc: Initial a7xx support
H A D21.0.0.rst1101 - freedreno: Fix uninitialized var warning in afuc using unreachable().
1104 - freedreno/afuc: Fix up some sprintf format security warnings.
3258 - freedreno/afuc: Replace readfile with os_read_file.
H A D20.2.0.rst1217 - freedreno/afuc: Add missing rnn_prepdb()
1218 - freedreno/afuc: Fix PM4 enum parsing
4178 - freedreno: slurp in afuc
4181 - freedreno/afuc: warnings cleanup
/aosp_15_r20/external/mesa3d/src/freedreno/
H A Dmeson.build43 subdir('afuc') subdir
/aosp_15_r20/external/mesa3d/
H A D.mr-label-maker.yml159 '^src/freedreno/afuc/': ['freedreno']

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