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/linux-6.14.4/drivers/gpu/drm/i915/display/
Dintel_cdclk.c2 * Copyright © 2006-2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
55 * The display engine uses several different clocks to do its work. There
58 * are the core display clock (CDCLK) and RAWCLK.
60 * CDCLK clocks most of the display pipe logic, and thus its frequency
66 * to minimize power consumption for a given display configuration.
67 * Typically changes to the CDCLK frequency require all the display pipes
77 * - We have the CDCLK PLL, which generates an output clock based on a
78 * reference clock and a ratio parameter.
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Dintel_display_power_well.c1 // SPDX-License-Identifier: MIT
49 void (*sync_hw)(struct intel_display *display,
53 * interrupts located on the well). Called after the 0->1 refcount
56 void (*enable)(struct intel_display *display,
60 * the 1->0 refcount transition.
62 void (*disable)(struct intel_display *display,
65 bool (*is_enabled)(struct intel_display *display,
72 return &power_well->desc->instances->list[power_well->instance_idx]; in i915_power_well_instance()
76 lookup_power_well(struct intel_display *display, in lookup_power_well() argument
81 for_each_power_well(display, power_well) in lookup_power_well()
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Dintel_dmc.c4 * Permission is hereby granted, free of charge, to any person obtaining a
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
38 * From gen9 onwards we have newly added DMC (Display microcontroller) in display
39 * engine to save and restore the state of display engine when it enter into
40 * low-power state and comes back to normal.
43 #define INTEL_DMC_FIRMWARE_URL "https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firm…
55 struct intel_display *display; member
73 static struct intel_dmc *display_to_dmc(struct intel_display *display) in display_to_dmc() argument
75 return display->dmc.dmc; in display_to_dmc()
78 static const char *dmc_firmware_param(struct intel_display *display) in dmc_firmware_param() argument
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Dintel_display_power.c1 /* SPDX-License-Identifier: MIT */
33 for_each_if(test_bit((__domain), (__power_well)->domains.bits))
37 for_each_if(test_bit((__domain), (__power_well)->domains.bits))
201 static bool __intel_display_power_is_enabled(struct intel_display *display, in __intel_display_power_is_enabled() argument
207 if (pm_runtime_suspended(display->drm->dev)) in __intel_display_power_is_enabled()
212 for_each_power_domain_well_reverse(display, power_well, domain) { in __intel_display_power_is_enabled()
226 * intel_display_power_is_enabled - check for a power domain
236 * threads can't disable the power well while the caller tries to read a few
245 struct intel_display *display = &dev_priv->display; in intel_display_power_is_enabled() local
246 struct i915_power_domains *power_domains = &display->power.domains; in intel_display_power_is_enabled()
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Dintel_display_reg_defs.h1 /* SPDX-License-Identifier: MIT */
11 #define DISPLAY_MMIO_BASE(dev_priv) (DISPLAY_INFO(dev_priv)->mmio_offset)
18 #define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b) argument
19 #define _PLANE(plane, a, b) _PICK_EVEN(plane, a, b) argument
20 #define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b) argument
21 #define _PORT(port, a, b) _PICK_EVEN(port, a, b) argument
22 #define _PLL(pll, a, b) _PICK_EVEN(pll, a, b) argument
23 #define _PHY(phy, a, b) _PICK_EVEN(phy, a, b) argument
25 #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b)) argument
26 #define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b)) argument
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Dvlv_dsi_regs.h1 /* SPDX-License-Identifier: MIT */
14 #define _MIPI_MMIO_BASE(display) ((display)->dsi.mmio_base) argument
16 #define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c) /* ports A and C only */ argument
17 #define _MMIO_MIPI(base, port, a, c) _MMIO((base) + _MIPI_PORT(port, a, c)) argument
47 #define DPI_ENABLE (1 << 31) /* A + C */
54 #define DITHERING_ENABLE (1 << 25) /* A + C */
75 #define TEARING_EFFECT_DELAY (1 << 4) /* A + C */
76 #define TEARING_EFFECT_SHIFT 2 /* A + C */
93 /* MIPI DSI Controller and D-PHY registers */
97 #define MIPI_DEVICE_READY(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DEVICE_R… argument
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Dvlv_dsi.c4 * Permission is hereby granted, free of charge, to any person obtaining a
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
89 struct intel_display *display = to_intel_display(&intel_dsi->base); in vlv_dsi_wait_for_fifo_empty() local
95 if (intel_de_wait_for_set(display, MIPI_GEN_FIFO_STAT(display, port), in vlv_dsi_wait_for_fifo_empty()
97 drm_err(display->drm, "DPI FIFOs are not empty\n"); in vlv_dsi_wait_for_fifo_empty()
100 static void write_data(struct intel_display *display, in write_data() argument
109 for (j = 0; j < min_t(u32, len - i, 4); j++) in write_data()
112 intel_de_write(display, reg, val); in write_data()
116 static void read_data(struct intel_display *display, in read_data() argument
123 u32 val = intel_de_read(display, reg); in read_data()
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Dintel_gmbus.c3 * Copyright © 2006-2008,2010 Intel Corporation
6 * Permission is hereby granted, free of charge, to any person obtaining a
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
27 * Chris Wilson <chris@chris-wilson.co.uk>
31 #include <linux/i2c-algo-bit.h>
34 #include <drm/display/drm_hdcp_helper.h>
51 struct intel_display *display; member
152 static const struct gmbus_pin *get_gmbus_pin(struct intel_display *display, in get_gmbus_pin() argument
155 struct drm_i915_private *i915 = to_i915(display->drm); in get_gmbus_pin()
177 } else if (DISPLAY_VER(display) == 9) { in get_gmbus_pin()
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Dintel_display_driver.c1 // SPDX-License-Identifier: MIT
3 * Copyright © 2022-2023 Intel Corporation
5 * High level display driver entry points. This is a layer between top level
6 * driver code and low level display functionality; no low level display code or
12 #include <drm/display/drm_dp_mst_helper.h>
67 * apple-gmux is needed on dual GPU MacBook Pro in intel_display_driver_probe_defer()
73 /* If the LCD panel has a privacy-screen, wait for it */ in intel_display_driver_probe_defer()
74 privacy_screen = drm_privacy_screen_get(&pdev->dev, NULL); in intel_display_driver_probe_defer()
75 if (IS_ERR(privacy_screen) && PTR_ERR(privacy_screen) == -EPROBE_DEFER) in intel_display_driver_probe_defer()
83 void intel_display_driver_init_hw(struct intel_display *display) in intel_display_driver_init_hw() argument
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Dintel_crt.c2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
90 bool intel_crt_port_enabled(struct intel_display *display, in intel_crt_port_enabled() argument
93 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_crt_port_enabled()
96 val = intel_de_read(display, adpa_reg); in intel_crt_port_enabled()
110 struct intel_display *display = to_intel_display(encoder); in intel_crt_get_hw_state() local
111 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_crt_get_hw_state()
117 encoder->power_domain); in intel_crt_get_hw_state()
121 ret = intel_crt_port_enabled(display, crt->adpa_reg, pipe); in intel_crt_get_hw_state()
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Dintel_dmc_wl.c1 // SPDX-License-Identifier: MIT
20 * Wake lock is the mechanism to cause display engine to exit DC
30 * The wakelock mechanism in DMC allows the display engine to exit DC
33 * implicitly when the display engine accessed a register. With the
34 * wakelock implementation, the driver asserts a wakelock in DMC,
144 static void __intel_dmc_wl_release(struct intel_display *display) in __intel_dmc_wl_release() argument
146 struct drm_i915_private *i915 = to_i915(display->drm); in __intel_dmc_wl_release()
147 struct intel_dmc_wl *wl = &display->wl; in __intel_dmc_wl_release()
149 WARN_ON(refcount_read(&wl->refcount)); in __intel_dmc_wl_release()
151 queue_delayed_work(i915->unordered_wq, &wl->work, in __intel_dmc_wl_release()
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Dintel_frontbuffer.c4 * Permission is hereby granted, free of charge, to any person obtaining a
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
33 * To be able to do so we track frontbuffers using a bitmask for all possible
37 * and when the frontbuffer is exchanged with a flip. Subsystems interested in
42 * On a high level there are two types of powersaving features. The first one
43 * work like a special cache (FBC and PSR) and are interested when they should
51 * The other type of display power saving feature only cares about busyness
73 * frontbuffer_flush - flush frontbuffer
88 struct intel_display *display = &i915->display; in frontbuffer_flush() local
91 spin_lock(&i915->display.fb_tracking.lock); in frontbuffer_flush()
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Dintel_vga.c1 // SPDX-License-Identifier: MIT
17 static i915_reg_t intel_vga_cntrl_reg(struct intel_display *display) in intel_vga_cntrl_reg() argument
19 if (display->platform.valleyview || display->platform.cherryview) in intel_vga_cntrl_reg()
21 else if (DISPLAY_VER(display) >= 5) in intel_vga_cntrl_reg()
28 void intel_vga_disable(struct intel_display *display) in intel_vga_disable() argument
30 struct pci_dev *pdev = to_pci_dev(display->drm->dev); in intel_vga_disable()
31 i915_reg_t vga_reg = intel_vga_cntrl_reg(display); in intel_vga_disable()
34 if (intel_de_read(display, vga_reg) & VGA_DISP_DISABLE) in intel_vga_disable()
45 intel_de_write(display, vga_reg, VGA_DISP_DISABLE); in intel_vga_disable()
46 intel_de_posting_read(display, vga_reg); in intel_vga_disable()
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Dintel_hotplug.c4 * Permission is hereby granted, free of charge, to any person obtaining a
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
39 * Simply put, hotplug occurs when a display is connected to or disconnected
41 * Display Port short pulses and MST devices involved, complicating matters.
48 * into a platform independent mask of hotplug pins that have fired.
52 * further processing to appropriate bottom halves (Display Port specific and
55 * The Display Port work function i915_digport_work_func() calls into
57 * pulses, with failures and non-MST long pulses triggering regular hotplug
64 * Finally, the userspace is responsible for triggering a modeset upon receiving
68 * number of interrupts per hotplug pin per a period of time, and if the number
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Dintel_psr.c4 * Permission is hereby granted, free of charge, to any person obtaining a
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
52 * Since Haswell Display controller supports Panel Self-Refresh on display
53 * panels witch have a remote frame buffer (RFB) implemented according to PSR
54 * spec in eDP1.3. PSR feature allows the display to go to lower standby states
55 * when system is idle but display is on as it eliminates display refresh
57 * display is unchanged.
66 * The implementation uses the hardware-based PSR support which automatically
67 * enters/exits self-refresh mode. The hardware takes care of sending the
70 * changes to know when to exit self-refresh mode again. Unfortunately that
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Dintel_pps.c1 // SPDX-License-Identifier: MIT
23 static void vlv_steal_power_sequencer(struct intel_display *display,
31 struct intel_display *display = to_intel_display(intel_dp); in pps_name() local
32 struct intel_pps *pps = &intel_dp->pps; in pps_name()
34 if (display->platform.valleyview || display->platform.cherryview) { in pps_name()
35 switch (pps->vlv_pps_pipe) { in pps_name()
39 * to always have a valid PPS when calling this. in pps_name()
43 return "PPS A"; in pps_name()
47 MISSING_CASE(pps->vlv_pps_pipe); in pps_name()
51 switch (pps->pps_idx) { in pps_name()
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Dintel_dp_tunnel.c1 // SPDX-License-Identifier: MIT
6 #include <drm/display/drm_dp_tunnel.h>
23 * intel_dp_tunnel_disconnect - Disconnect a DP tunnel from a port
26 * Disconnect a DP tunnel from @intel_dp, destroying any related state. This
27 * should be called after detecting a sink-disconnect event from the port.
31 drm_dp_tunnel_destroy(intel_dp->tunnel); in intel_dp_tunnel_disconnect()
32 intel_dp->tunnel = NULL; in intel_dp_tunnel_disconnect()
36 * intel_dp_tunnel_destroy - Destroy a DP tunnel
39 * Destroy a DP tunnel connected to @intel_dp, after disabling the BW
46 drm_dp_tunnel_disable_bw_alloc(intel_dp->tunnel); in intel_dp_tunnel_destroy()
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/linux-6.14.4/drivers/media/platform/renesas/vsp1/
Dvsp1_dl.c1 // SPDX-License-Identifier: GPL-2.0+
3 * vsp1_dl.c -- R-Car VSP1 Display List
11 #include <linux/dma-mapping.h>
41 * struct vsp1_dl_ext_header - Extended display list header
43 * @pre_ext_dl_num_cmd: number of pre-extended command bodies to parse
45 * @pre_ext_dl_plist: start address of pre-extended display list bodies
46 * @post_ext_dl_num_cmd: number of post-extended command bodies to parse
47 * @post_ext_dl_plist: start address of post-extended display list bodies
54 * expecting 32-bit accesses. The flags are appropriate to the whole
79 * struct vsp1_pre_ext_dl_body - Pre Extended Display List Body
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/linux-6.14.4/Documentation/gpu/amdgpu/display/
Ddc-debug.rst2 Display Core Debug tools
6 driver from the display perspective. This page introduces debug mechanisms and
7 procedures to help you identify if some issues are related to display code.
9 Narrow down display issues
12 Since the display is the driver's visual component, it is common to see users
13 reporting issues as a display when another component causes the problem. This
14 section equips users to determine if a specific issue was caused by the display
18 ---------------------------
43 (**Display Manager**), was loaded, which means that display can be part of the
45 amdgpu loads the display component, indicating that we don't have a
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Dindex.rst1 .. _amdgpu-display-core:
4 drm/amd/display - Display Core (DC)
7 AMD display engine is partially shared with other operating systems; for this
8 reason, our Display Core Driver is divided into two pieces:
10 #. **Display Core (DC)** contains the OS-agnostic components. Things like
12 #. **Display Manager (DM)** contains the OS-dependent components. Hooks to the
14 display/amdgpu_dm/ folder.
16 ------------------
18 ------------------
20 Maintaining the same code base across multiple OSes requires a lot of
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Ddcn-overview.rst4 Display Core Next (DCN)
7 To equip our readers with the basic knowledge of how AMD Display Core Next
9 you can see a picture that provides a DCN overview, keep in mind that this is a
12 .. kernel-figure:: dc_pipeline_overview.svg
17 * **Display Controller Hub (DCHUB)**: This is the gateway between the Scalable
21 * **Display Pipe and Plane (DPP)**: This block provides pre-blend pixel
26 multiple planes, using global or per-pixel alpha.
29 the display.
34 * **Display Output (DIO)**: Codify the output to the display connected to our
37 * **Display Writeback (DWB)**: It provides the ability to write the output of
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/linux-6.14.4/Documentation/devicetree/bindings/display/
Dsimple-framebuffer.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/simple-framebuffer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hans de Goede <[email protected]>
13 A simple frame-buffer describes a frame-buffer setup by firmware or
14 the bootloader, with the assumption that the display hardware has
19 sub-nodes of the chosen node (*). Simplefb nodes must be named
22 If the devicetree contains nodes for the display hardware used by a
23 simplefb, then the simplefb node must contain a property called
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Dxylon,logicvc-display.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/xylon,logicvc-display.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Xylon LogiCVC display controller
11 - Paul Kocialkowski <[email protected]>
14 The Xylon LogiCVC is a display controller that supports multiple layers.
16 with Xilinx Zynq-7000 SoCs and Xilinx FPGAs.
18 Because the controller is intended for use in a FPGA, most of the
20 synthesis time. As a result, many of the device-tree bindings are meant to
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/linux-6.14.4/Documentation/devicetree/bindings/display/panel/
Dpanel-common.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/panel/panel-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common Properties for Display Panels
10 - Thierry Reding <[email protected]>
11 - Laurent Pinchart <[email protected]>
15 display panels. It doesn't constitute a device tree binding specification by
24 width-mm:
29 height-mm:
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/linux-6.14.4/drivers/gpu/drm/i915/
Di915_driver.c1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
8 * Permission is hereby granted, free of charge, to any person obtaining a
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
48 #include "display/i9xx_display_sr.h"
49 #include "display/intel_acpi.h"
50 #include "display/intel_bw.h"
51 #include "display/intel_cdclk.h"
52 #include "display/intel_crtc.h"
53 #include "display/intel_display_driver.h"
54 #include "display/intel_dmc.h"
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