Lines Matching +full:a +full:- +full:display
4 * Permission is hereby granted, free of charge, to any person obtaining a
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
89 struct intel_display *display = to_intel_display(&intel_dsi->base); in vlv_dsi_wait_for_fifo_empty() local
95 if (intel_de_wait_for_set(display, MIPI_GEN_FIFO_STAT(display, port), in vlv_dsi_wait_for_fifo_empty()
97 drm_err(display->drm, "DPI FIFOs are not empty\n"); in vlv_dsi_wait_for_fifo_empty()
100 static void write_data(struct intel_display *display, in write_data() argument
109 for (j = 0; j < min_t(u32, len - i, 4); j++) in write_data()
112 intel_de_write(display, reg, val); in write_data()
116 static void read_data(struct intel_display *display, in read_data() argument
123 u32 val = intel_de_read(display, reg); in read_data()
125 for (j = 0; j < min_t(u32, len - i, 4); j++) in read_data()
134 struct intel_dsi *intel_dsi = intel_dsi_host->intel_dsi; in intel_dsi_host_transfer()
135 struct intel_display *display = to_intel_display(&intel_dsi->base); in intel_dsi_host_transfer() local
136 enum port port = intel_dsi_host->port; in intel_dsi_host_transfer()
149 if (msg->flags & MIPI_DSI_MSG_USE_LPM) { in intel_dsi_host_transfer()
150 data_reg = MIPI_LP_GEN_DATA(display, port); in intel_dsi_host_transfer()
152 ctrl_reg = MIPI_LP_GEN_CTRL(display, port); in intel_dsi_host_transfer()
155 data_reg = MIPI_HS_GEN_DATA(display, port); in intel_dsi_host_transfer()
157 ctrl_reg = MIPI_HS_GEN_CTRL(display, port); in intel_dsi_host_transfer()
163 if (intel_de_wait_for_clear(display, MIPI_GEN_FIFO_STAT(display, port), in intel_dsi_host_transfer()
165 drm_err(display->drm, in intel_dsi_host_transfer()
168 write_data(display, data_reg, packet.payload, in intel_dsi_host_transfer()
172 if (msg->rx_len) { in intel_dsi_host_transfer()
173 intel_de_write(display, MIPI_INTR_STAT(display, port), in intel_dsi_host_transfer()
177 if (intel_de_wait_for_clear(display, MIPI_GEN_FIFO_STAT(display, port), in intel_dsi_host_transfer()
179 drm_err(display->drm, in intel_dsi_host_transfer()
183 intel_de_write(display, ctrl_reg, in intel_dsi_host_transfer()
186 /* ->rx_len is set only for reads */ in intel_dsi_host_transfer()
187 if (msg->rx_len) { in intel_dsi_host_transfer()
189 if (intel_de_wait_for_set(display, MIPI_INTR_STAT(display, port), in intel_dsi_host_transfer()
191 drm_err(display->drm, in intel_dsi_host_transfer()
194 read_data(display, data_reg, msg->rx_buf, msg->rx_len); in intel_dsi_host_transfer()
220 * send a video mode command
227 struct intel_display *display = to_intel_display(&intel_dsi->base); in dpi_send_cmd() local
237 intel_de_write(display, MIPI_INTR_STAT(display, port), SPL_PKT_SENT_INTERRUPT); in dpi_send_cmd()
240 if (cmd == intel_de_read(display, MIPI_DPI_CONTROL(display, port))) in dpi_send_cmd()
241 drm_dbg_kms(display->drm, in dpi_send_cmd()
242 "Same special packet %02x twice in a row.\n", cmd); in dpi_send_cmd()
244 intel_de_write(display, MIPI_DPI_CONTROL(display, port), cmd); in dpi_send_cmd()
247 if (intel_de_wait_for_set(display, MIPI_INTR_STAT(display, port), mask, 100)) in dpi_send_cmd()
248 drm_err(display->drm, in dpi_send_cmd()
272 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_compute_config()
274 struct intel_connector *intel_connector = intel_dsi->attached_connector; in intel_dsi_compute_config()
275 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; in intel_dsi_compute_config()
278 drm_dbg_kms(&dev_priv->drm, "\n"); in intel_dsi_compute_config()
279 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; in intel_dsi_compute_config()
280 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; in intel_dsi_compute_config()
290 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) in intel_dsi_compute_config()
291 return -EINVAL; in intel_dsi_compute_config()
294 adjusted_mode->flags = 0; in intel_dsi_compute_config()
296 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888) in intel_dsi_compute_config()
297 pipe_config->pipe_bpp = 24; in intel_dsi_compute_config()
299 pipe_config->pipe_bpp = 18; in intel_dsi_compute_config()
303 pipe_config->mode_flags |= in intel_dsi_compute_config()
306 /* Dual link goes to DSI transcoder A. */ in intel_dsi_compute_config()
307 if (intel_dsi->ports == BIT(PORT_C)) in intel_dsi_compute_config()
308 pipe_config->cpu_transcoder = TRANSCODER_DSI_C; in intel_dsi_compute_config()
310 pipe_config->cpu_transcoder = TRANSCODER_DSI_A; in intel_dsi_compute_config()
314 return -EINVAL; in intel_dsi_compute_config()
318 return -EINVAL; in intel_dsi_compute_config()
321 pipe_config->clock_set = true; in intel_dsi_compute_config()
328 struct intel_display *display = to_intel_display(encoder); in glk_dsi_enable_io() local
337 for_each_dsi_port(port, intel_dsi->ports) in glk_dsi_enable_io()
338 intel_de_rmw(display, MIPI_CTRL(display, port), 0, GLK_MIPIIO_ENABLE); in glk_dsi_enable_io()
341 intel_de_rmw(display, MIPI_CTRL(display, PORT_A), GLK_MIPIIO_RESET_RELEASED, 0); in glk_dsi_enable_io()
344 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_enable_io()
345 u32 tmp = intel_de_read(display, MIPI_DEVICE_READY(display, port)); in glk_dsi_enable_io()
347 intel_de_rmw(display, MIPI_CTRL(display, port), in glk_dsi_enable_io()
352 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_enable_io()
353 if (intel_de_wait_for_set(display, MIPI_CTRL(display, port), in glk_dsi_enable_io()
355 drm_err(display->drm, "MIPIO port is powergated\n"); in glk_dsi_enable_io()
359 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_enable_io()
361 !(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY); in glk_dsi_enable_io()
369 struct intel_display *display = to_intel_display(encoder); in glk_dsi_device_ready() local
374 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_device_ready()
375 if (intel_de_wait_for_set(display, MIPI_CTRL(display, port), in glk_dsi_device_ready()
377 drm_err(display->drm, "PHY is not ON\n"); in glk_dsi_device_ready()
381 intel_de_rmw(display, MIPI_CTRL(display, PORT_A), 0, GLK_MIPIIO_RESET_RELEASED); in glk_dsi_device_ready()
384 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_device_ready()
385 if (!(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY)) { in glk_dsi_device_ready()
386 intel_de_rmw(display, MIPI_DEVICE_READY(display, port), in glk_dsi_device_ready()
391 intel_de_rmw(display, MIPI_DEVICE_READY(display, port), in glk_dsi_device_ready()
395 if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port), in glk_dsi_device_ready()
397 drm_err(display->drm, "ULPS not active\n"); in glk_dsi_device_ready()
400 intel_de_rmw(display, MIPI_DEVICE_READY(display, port), in glk_dsi_device_ready()
404 intel_de_rmw(display, MIPI_DEVICE_READY(display, port), in glk_dsi_device_ready()
408 intel_de_rmw(display, MIPI_CTRL(display, port), GLK_LP_WAKE, 0); in glk_dsi_device_ready()
413 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_device_ready()
414 if (intel_de_wait_for_set(display, MIPI_CTRL(display, port), in glk_dsi_device_ready()
416 drm_err(display->drm, in glk_dsi_device_ready()
421 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_device_ready()
422 if (intel_de_wait_for_set(display, BXT_MIPI_PORT_CTRL(port), in glk_dsi_device_ready()
424 drm_err(display->drm, in glk_dsi_device_ready()
425 "D-PHY not entering LP-11 state\n"); in glk_dsi_device_ready()
431 struct intel_display *display = to_intel_display(encoder); in bxt_dsi_device_ready() local
436 drm_dbg_kms(display->drm, "\n"); in bxt_dsi_device_ready()
439 for_each_dsi_port(port, intel_dsi->ports) { in bxt_dsi_device_ready()
440 intel_de_rmw(display, BXT_MIPI_PORT_CTRL(port), 0, LP_OUTPUT_HOLD); in bxt_dsi_device_ready()
445 for_each_dsi_port(port, intel_dsi->ports) { in bxt_dsi_device_ready()
446 val = intel_de_read(display, MIPI_DEVICE_READY(display, port)); in bxt_dsi_device_ready()
448 intel_de_write(display, MIPI_DEVICE_READY(display, port), val); in bxt_dsi_device_ready()
451 intel_de_write(display, MIPI_DEVICE_READY(display, port), val); in bxt_dsi_device_ready()
457 struct intel_display *display = to_intel_display(encoder); in vlv_dsi_device_ready() local
458 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in vlv_dsi_device_ready()
462 drm_dbg_kms(display->drm, "\n"); in vlv_dsi_device_ready()
473 for_each_dsi_port(port, intel_dsi->ports) { in vlv_dsi_device_ready()
475 intel_de_write(display, MIPI_DEVICE_READY(display, port), in vlv_dsi_device_ready()
480 * Common bit for both MIPI Port A & MIPI Port C in vlv_dsi_device_ready()
483 intel_de_rmw(display, VLV_MIPI_PORT_CTRL(PORT_A), 0, LP_OUTPUT_HOLD); in vlv_dsi_device_ready()
486 intel_de_write(display, MIPI_DEVICE_READY(display, port), in vlv_dsi_device_ready()
490 intel_de_write(display, MIPI_DEVICE_READY(display, port), in vlv_dsi_device_ready()
498 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_device_ready()
510 struct intel_display *display = to_intel_display(encoder); in glk_dsi_enter_low_power_mode() local
515 for_each_dsi_port(port, intel_dsi->ports) in glk_dsi_enter_low_power_mode()
516 intel_de_rmw(display, MIPI_DEVICE_READY(display, port), in glk_dsi_enter_low_power_mode()
520 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_enter_low_power_mode()
521 if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port), in glk_dsi_enter_low_power_mode()
523 drm_err(display->drm, "PHY is not turning OFF\n"); in glk_dsi_enter_low_power_mode()
527 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_enter_low_power_mode()
528 if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port), in glk_dsi_enter_low_power_mode()
530 drm_err(display->drm, in glk_dsi_enter_low_power_mode()
537 struct intel_display *display = to_intel_display(encoder); in glk_dsi_disable_mipi_io() local
542 intel_de_rmw(display, MIPI_CTRL(display, PORT_A), GLK_MIPIIO_RESET_RELEASED, 0); in glk_dsi_disable_mipi_io()
545 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_disable_mipi_io()
546 if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port), in glk_dsi_disable_mipi_io()
548 drm_err(display->drm, "PHY is not turning OFF\n"); in glk_dsi_disable_mipi_io()
552 for_each_dsi_port(port, intel_dsi->ports) in glk_dsi_disable_mipi_io()
553 intel_de_rmw(display, MIPI_CTRL(display, port), GLK_MIPIIO_ENABLE, 0); in glk_dsi_disable_mipi_io()
570 struct intel_display *display = to_intel_display(encoder); in vlv_dsi_clear_device_ready() local
571 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in vlv_dsi_clear_device_ready()
575 drm_dbg_kms(display->drm, "\n"); in vlv_dsi_clear_device_ready()
576 for_each_dsi_port(port, intel_dsi->ports) { in vlv_dsi_clear_device_ready()
577 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */ in vlv_dsi_clear_device_ready()
581 intel_de_write(display, MIPI_DEVICE_READY(display, port), in vlv_dsi_clear_device_ready()
585 intel_de_write(display, MIPI_DEVICE_READY(display, port), in vlv_dsi_clear_device_ready()
589 intel_de_write(display, MIPI_DEVICE_READY(display, port), in vlv_dsi_clear_device_ready()
594 * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI in vlv_dsi_clear_device_ready()
595 * Port A only. MIPI Port C has no similar bit for checking. in vlv_dsi_clear_device_ready()
598 intel_de_wait_for_clear(display, port_ctrl, in vlv_dsi_clear_device_ready()
600 drm_err(display->drm, "DSI LP not going Low\n"); in vlv_dsi_clear_device_ready()
603 intel_de_rmw(display, port_ctrl, LP_OUTPUT_HOLD, 0); in vlv_dsi_clear_device_ready()
606 intel_de_write(display, MIPI_DEVICE_READY(display, port), 0x00); in vlv_dsi_clear_device_ready()
614 struct intel_display *display = to_intel_display(encoder); in intel_dsi_port_enable() local
615 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_port_enable()
616 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_dsi_port_enable()
620 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { in intel_dsi_port_enable()
621 u32 temp = intel_dsi->pixel_overlap; in intel_dsi_port_enable()
624 for_each_dsi_port(port, intel_dsi->ports) in intel_dsi_port_enable()
625 intel_de_rmw(display, MIPI_CTRL(display, port), in intel_dsi_port_enable()
629 intel_de_rmw(display, VLV_CHICKEN_3, in intel_dsi_port_enable()
635 for_each_dsi_port(port, intel_dsi->ports) { in intel_dsi_port_enable()
639 temp = intel_de_read(display, port_ctrl); in intel_dsi_port_enable()
644 if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) { in intel_dsi_port_enable()
645 temp |= (intel_dsi->dual_link - 1) in intel_dsi_port_enable()
650 temp |= crtc->pipe ? in intel_dsi_port_enable()
655 if (intel_dsi->pixel_format != MIPI_DSI_FMT_RGB888) in intel_dsi_port_enable()
659 intel_de_write(display, port_ctrl, temp | DPI_ENABLE); in intel_dsi_port_enable()
660 intel_de_posting_read(display, port_ctrl); in intel_dsi_port_enable()
666 struct intel_display *display = to_intel_display(encoder); in intel_dsi_port_disable() local
667 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_port_disable()
671 for_each_dsi_port(port, intel_dsi->ports) { in intel_dsi_port_disable()
674 /* de-assert ip_tg_enable signal */ in intel_dsi_port_disable()
675 intel_de_rmw(display, port_ctrl, DPI_ENABLE, 0); in intel_dsi_port_disable()
676 intel_de_posting_read(display, port_ctrl); in intel_dsi_port_disable()
692 * VBTs several steps which have a VBT in v2 are expected to be handled
696 * - power on - MIPIPanelPowerOn - power on
697 * - wait t1+t2 - wait t1+t2
698 * - MIPIDeassertResetPin - MIPIDeassertResetPin - MIPIDeassertResetPin
699 * - io lines to lp-11 - io lines to lp-11 - io lines to lp-11
700 * - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds
701 * - MIPITearOn
702 * - MIPIDisplayOn
703 * - turn on DPI - turn on DPI - set pipe to dsr mode
704 * - MIPIDisplayOn - MIPIDisplayOn
705 * - wait t5 - wait t5
706 * - backlight on - MIPIBacklightOn - backlight on
708 * - backlight off - MIPIBacklightOff - backlight off
709 * - wait t6 - wait t6
710 * - MIPIDisplayOff
711 * - turn off DPI - turn off DPI - disable pipe dsr mode
712 * - MIPITearOff
713 * - MIPIDisplayOff - MIPIDisplayOff
714 * - io lines to lp-00 - io lines to lp-00 - io lines to lp-00
715 * - MIPIAssertResetPin - MIPIAssertResetPin - MIPIAssertResetPin
716 * - wait t3 - wait t3
717 * - power off - MIPIPanelPowerOff - power off
718 * - wait t4 - wait t4
730 struct intel_display *display = to_intel_display(encoder); in intel_dsi_pre_enable() local
732 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in intel_dsi_pre_enable()
733 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_dsi_pre_enable()
734 enum pipe pipe = crtc->pipe; in intel_dsi_pre_enable()
738 drm_dbg_kms(display->drm, "\n"); in intel_dsi_pre_enable()
745 * The BIOS may leave the PLL in a wonky state where it doesn't in intel_dsi_pre_enable()
758 intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, 0, MIPIO_RST_CTRL); in intel_dsi_pre_enable()
761 intel_de_write(display, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); in intel_dsi_pre_enable()
762 intel_de_write(display, BXT_P_DSI_REGULATOR_TX_CTRL, 0); in intel_dsi_pre_enable()
767 intel_de_rmw(display, DSPCLK_GATE_D(dev_priv), in intel_dsi_pre_enable()
774 /* Give the panel time to power-on and then deassert its reset */ in intel_dsi_pre_enable()
776 msleep(intel_dsi->panel_on_delay); in intel_dsi_pre_enable()
787 /* Put device in ready state (LP-11) */ in intel_dsi_pre_enable()
798 * Enable port in pre-enable phase itself because as per hw team in intel_dsi_pre_enable()
802 for_each_dsi_port(port, intel_dsi->ports) in intel_dsi_pre_enable()
803 intel_de_write(display, in intel_dsi_pre_enable()
804 MIPI_MAX_RETURN_PKT_SIZE(display, port), 8 * 4); in intel_dsi_pre_enable()
809 for_each_dsi_port(port, intel_dsi->ports) in intel_dsi_pre_enable()
839 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_dsi_disable()
843 drm_dbg_kms(&i915->drm, "\n"); in intel_dsi_disable()
855 for_each_dsi_port(port, intel_dsi->ports) in intel_dsi_disable()
863 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_clear_device_ready()
876 struct intel_display *display = to_intel_display(encoder); in intel_dsi_post_disable() local
877 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_post_disable()
881 drm_dbg_kms(display->drm, "\n"); in intel_dsi_post_disable()
890 for_each_dsi_port(port, intel_dsi->ports) in intel_dsi_post_disable()
907 /* Transition to LP-00 */ in intel_dsi_post_disable()
912 intel_de_write(display, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); in intel_dsi_post_disable()
913 intel_de_write(display, BXT_P_DSI_REGULATOR_TX_CTRL, in intel_dsi_post_disable()
917 intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, MIPIO_RST_CTRL, 0); in intel_dsi_post_disable()
925 intel_de_rmw(display, DSPCLK_GATE_D(dev_priv), in intel_dsi_post_disable()
932 msleep(intel_dsi->panel_off_delay); in intel_dsi_post_disable()
935 intel_dsi->panel_power_off_time = ktime_get_boottime(); in intel_dsi_post_disable()
941 struct intel_display *display = to_intel_display(encoder); in intel_dsi_get_hw_state() local
942 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_get_hw_state()
948 drm_dbg_kms(display->drm, "\n"); in intel_dsi_get_hw_state()
951 encoder->power_domain); in intel_dsi_get_hw_state()
956 * On Broxton the PLL needs to be enabled with a valid divider in intel_dsi_get_hw_state()
958 * machine. See BSpec North Display Engine registers/MIPI[BXT]. in intel_dsi_get_hw_state()
965 for_each_dsi_port(port, intel_dsi->ports) { in intel_dsi_get_hw_state()
967 bool enabled = intel_de_read(display, port_ctrl) & DPI_ENABLE; in intel_dsi_get_hw_state()
971 * bit in port C control register does not get set. As a in intel_dsi_get_hw_state()
976 enabled = intel_de_read(display, in intel_dsi_get_hw_state()
981 u32 tmp = intel_de_read(display, in intel_dsi_get_hw_state()
982 MIPI_DSI_FUNC_PRG(display, port)); in intel_dsi_get_hw_state()
989 if (!(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY)) in intel_dsi_get_hw_state()
993 u32 tmp = intel_de_read(display, MIPI_CTRL(display, port)); in intel_dsi_get_hw_state()
997 if (drm_WARN_ON(display->drm, tmp > PIPE_C)) in intel_dsi_get_hw_state()
1010 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); in intel_dsi_get_hw_state()
1018 struct intel_display *display = to_intel_display(encoder); in bxt_dsi_get_pipe_config() local
1020 &pipe_config->hw.adjusted_mode; in bxt_dsi_get_pipe_config()
1022 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in bxt_dsi_get_pipe_config()
1024 unsigned int lane_count = intel_dsi->lane_count; in bxt_dsi_get_pipe_config()
1033 adjusted_mode_sw = &crtc->config->hw.adjusted_mode; in bxt_dsi_get_pipe_config()
1036 * Atleast one port is active as encoder->get_config called only if in bxt_dsi_get_pipe_config()
1037 * encoder->get_hw_state() returns true. in bxt_dsi_get_pipe_config()
1039 for_each_dsi_port(port, intel_dsi->ports) { in bxt_dsi_get_pipe_config()
1040 if (intel_de_read(display, BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE) in bxt_dsi_get_pipe_config()
1044 fmt = intel_de_read(display, MIPI_DSI_FUNC_PRG(display, port)) & VID_MODE_FORMAT_MASK; in bxt_dsi_get_pipe_config()
1048 pipe_config->pipe_bpp = bdw_get_pipe_misc_bpp(crtc); in bxt_dsi_get_pipe_config()
1051 pipe_config->mode_flags |= in bxt_dsi_get_pipe_config()
1055 adjusted_mode->crtc_hdisplay = in bxt_dsi_get_pipe_config()
1056 intel_de_read(display, in bxt_dsi_get_pipe_config()
1058 adjusted_mode->crtc_vdisplay = in bxt_dsi_get_pipe_config()
1059 intel_de_read(display, in bxt_dsi_get_pipe_config()
1061 adjusted_mode->crtc_vtotal = in bxt_dsi_get_pipe_config()
1062 intel_de_read(display, in bxt_dsi_get_pipe_config()
1065 hactive = adjusted_mode->crtc_hdisplay; in bxt_dsi_get_pipe_config()
1066 hfp = intel_de_read(display, MIPI_HFP_COUNT(display, port)); in bxt_dsi_get_pipe_config()
1069 * Meaningful for video mode non-burst sync pulse mode only, in bxt_dsi_get_pipe_config()
1070 * can be zero for non-burst sync events and burst modes in bxt_dsi_get_pipe_config()
1072 hsync = intel_de_read(display, MIPI_HSYNC_PADDING_COUNT(display, port)); in bxt_dsi_get_pipe_config()
1073 hbp = intel_de_read(display, MIPI_HBP_COUNT(display, port)); in bxt_dsi_get_pipe_config()
1077 intel_dsi->burst_mode_ratio); in bxt_dsi_get_pipe_config()
1079 intel_dsi->burst_mode_ratio); in bxt_dsi_get_pipe_config()
1081 intel_dsi->burst_mode_ratio); in bxt_dsi_get_pipe_config()
1083 if (intel_dsi->dual_link) { in bxt_dsi_get_pipe_config()
1090 vfp = intel_de_read(display, MIPI_VFP_COUNT(display, port)); in bxt_dsi_get_pipe_config()
1091 vsync = intel_de_read(display, MIPI_VSYNC_PADDING_COUNT(display, port)); in bxt_dsi_get_pipe_config()
1093 adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp; in bxt_dsi_get_pipe_config()
1094 adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay; in bxt_dsi_get_pipe_config()
1095 adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start; in bxt_dsi_get_pipe_config()
1096 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; in bxt_dsi_get_pipe_config()
1097 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; in bxt_dsi_get_pipe_config()
1099 adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay; in bxt_dsi_get_pipe_config()
1100 adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start; in bxt_dsi_get_pipe_config()
1101 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; in bxt_dsi_get_pipe_config()
1102 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; in bxt_dsi_get_pipe_config()
1116 hfp_sw = adjusted_mode_sw->crtc_hsync_start - in bxt_dsi_get_pipe_config()
1117 adjusted_mode_sw->crtc_hdisplay; in bxt_dsi_get_pipe_config()
1118 hsync_sw = adjusted_mode_sw->crtc_hsync_end - in bxt_dsi_get_pipe_config()
1119 adjusted_mode_sw->crtc_hsync_start; in bxt_dsi_get_pipe_config()
1120 hbp_sw = adjusted_mode_sw->crtc_htotal - in bxt_dsi_get_pipe_config()
1121 adjusted_mode_sw->crtc_hsync_end; in bxt_dsi_get_pipe_config()
1123 if (intel_dsi->dual_link) { in bxt_dsi_get_pipe_config()
1130 intel_dsi->burst_mode_ratio); in bxt_dsi_get_pipe_config()
1132 intel_dsi->burst_mode_ratio); in bxt_dsi_get_pipe_config()
1134 intel_dsi->burst_mode_ratio); in bxt_dsi_get_pipe_config()
1138 intel_dsi->burst_mode_ratio); in bxt_dsi_get_pipe_config()
1140 intel_dsi->burst_mode_ratio); in bxt_dsi_get_pipe_config()
1142 intel_dsi->burst_mode_ratio); in bxt_dsi_get_pipe_config()
1144 if (intel_dsi->dual_link) { in bxt_dsi_get_pipe_config()
1150 crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw + in bxt_dsi_get_pipe_config()
1152 crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay; in bxt_dsi_get_pipe_config()
1154 crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay; in bxt_dsi_get_pipe_config()
1157 if (adjusted_mode->crtc_htotal == crtc_htotal_sw) in bxt_dsi_get_pipe_config()
1158 adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal; in bxt_dsi_get_pipe_config()
1160 if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw) in bxt_dsi_get_pipe_config()
1161 adjusted_mode->crtc_hsync_start = in bxt_dsi_get_pipe_config()
1162 adjusted_mode_sw->crtc_hsync_start; in bxt_dsi_get_pipe_config()
1164 if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw) in bxt_dsi_get_pipe_config()
1165 adjusted_mode->crtc_hsync_end = in bxt_dsi_get_pipe_config()
1166 adjusted_mode_sw->crtc_hsync_end; in bxt_dsi_get_pipe_config()
1168 if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw) in bxt_dsi_get_pipe_config()
1169 adjusted_mode->crtc_hblank_start = in bxt_dsi_get_pipe_config()
1170 adjusted_mode_sw->crtc_hblank_start; in bxt_dsi_get_pipe_config()
1172 if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw) in bxt_dsi_get_pipe_config()
1173 adjusted_mode->crtc_hblank_end = in bxt_dsi_get_pipe_config()
1174 adjusted_mode_sw->crtc_hblank_end; in bxt_dsi_get_pipe_config()
1180 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_get_config()
1184 drm_dbg_kms(&dev_priv->drm, "\n"); in intel_dsi_get_config()
1186 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); in intel_dsi_get_config()
1195 pipe_config->port_clock = pclk; in intel_dsi_get_config()
1198 pipe_config->hw.adjusted_mode.crtc_clock = pclk; in intel_dsi_get_config()
1199 if (intel_dsi->dual_link) in intel_dsi_get_config()
1200 pipe_config->hw.adjusted_mode.crtc_clock *= 2; in intel_dsi_get_config()
1220 struct intel_display *display = to_intel_display(encoder); in set_dsi_timings() local
1221 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in set_dsi_timings()
1224 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); in set_dsi_timings()
1225 unsigned int lane_count = intel_dsi->lane_count; in set_dsi_timings()
1229 hactive = adjusted_mode->crtc_hdisplay; in set_dsi_timings()
1230 hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay; in set_dsi_timings()
1231 hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; in set_dsi_timings()
1232 hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end; in set_dsi_timings()
1234 if (intel_dsi->dual_link) { in set_dsi_timings()
1236 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) in set_dsi_timings()
1237 hactive += intel_dsi->pixel_overlap; in set_dsi_timings()
1243 vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay; in set_dsi_timings()
1244 vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start; in set_dsi_timings()
1245 vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end; in set_dsi_timings()
1249 intel_dsi->burst_mode_ratio); in set_dsi_timings()
1250 hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio); in set_dsi_timings()
1252 intel_dsi->burst_mode_ratio); in set_dsi_timings()
1253 hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); in set_dsi_timings()
1255 for_each_dsi_port(port, intel_dsi->ports) { in set_dsi_timings()
1263 intel_de_write(display, BXT_MIPI_TRANS_HACTIVE(port), in set_dsi_timings()
1264 adjusted_mode->crtc_hdisplay); in set_dsi_timings()
1265 intel_de_write(display, BXT_MIPI_TRANS_VACTIVE(port), in set_dsi_timings()
1266 adjusted_mode->crtc_vdisplay); in set_dsi_timings()
1267 intel_de_write(display, BXT_MIPI_TRANS_VTOTAL(port), in set_dsi_timings()
1268 adjusted_mode->crtc_vtotal); in set_dsi_timings()
1271 intel_de_write(display, MIPI_HACTIVE_AREA_COUNT(display, port), in set_dsi_timings()
1273 intel_de_write(display, MIPI_HFP_COUNT(display, port), hfp); in set_dsi_timings()
1275 /* meaningful for video mode non-burst sync pulse mode only, in set_dsi_timings()
1276 * can be zero for non-burst sync events and burst modes */ in set_dsi_timings()
1277 intel_de_write(display, MIPI_HSYNC_PADDING_COUNT(display, port), in set_dsi_timings()
1279 intel_de_write(display, MIPI_HBP_COUNT(display, port), hbp); in set_dsi_timings()
1282 intel_de_write(display, MIPI_VFP_COUNT(display, port), vfp); in set_dsi_timings()
1283 intel_de_write(display, MIPI_VSYNC_PADDING_COUNT(display, port), in set_dsi_timings()
1285 intel_de_write(display, MIPI_VBP_COUNT(display, port), vbp); in set_dsi_timings()
1309 struct intel_display *display = to_intel_display(encoder); in intel_dsi_prepare() local
1310 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_prepare()
1311 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in intel_dsi_prepare()
1313 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; in intel_dsi_prepare()
1315 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); in intel_dsi_prepare()
1319 drm_dbg_kms(display->drm, "pipe %c\n", pipe_name(crtc->pipe)); in intel_dsi_prepare()
1321 mode_hdisplay = adjusted_mode->crtc_hdisplay; in intel_dsi_prepare()
1323 if (intel_dsi->dual_link) { in intel_dsi_prepare()
1325 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) in intel_dsi_prepare()
1326 mode_hdisplay += intel_dsi->pixel_overlap; in intel_dsi_prepare()
1329 for_each_dsi_port(port, intel_dsi->ports) { in intel_dsi_prepare()
1332 * escape clock divider, 20MHz, shared for A and C. in intel_dsi_prepare()
1335 tmp = intel_de_read(display, MIPI_CTRL(display, PORT_A)); in intel_dsi_prepare()
1337 intel_de_write(display, MIPI_CTRL(display, PORT_A), in intel_dsi_prepare()
1341 tmp = intel_de_read(display, MIPI_CTRL(display, port)); in intel_dsi_prepare()
1343 intel_de_write(display, MIPI_CTRL(display, port), in intel_dsi_prepare()
1346 enum pipe pipe = crtc->pipe; in intel_dsi_prepare()
1348 intel_de_rmw(display, MIPI_CTRL(display, port), in intel_dsi_prepare()
1353 intel_de_write(display, MIPI_INTR_STAT(display, port), 0xffffffff); in intel_dsi_prepare()
1354 intel_de_write(display, MIPI_INTR_EN(display, port), 0xffffffff); in intel_dsi_prepare()
1356 intel_de_write(display, MIPI_DPHY_PARAM(display, port), in intel_dsi_prepare()
1357 intel_dsi->dphy_reg); in intel_dsi_prepare()
1359 intel_de_write(display, MIPI_DPI_RESOLUTION(display, port), in intel_dsi_prepare()
1360 …adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT… in intel_dsi_prepare()
1365 val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT; in intel_dsi_prepare()
1367 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT; in intel_dsi_prepare()
1370 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT; in intel_dsi_prepare()
1371 val |= pixel_format_to_reg(intel_dsi->pixel_format); in intel_dsi_prepare()
1375 if (intel_dsi->eotp_pkt == 0) in intel_dsi_prepare()
1377 if (intel_dsi->clock_stop) in intel_dsi_prepare()
1386 for_each_dsi_port(port, intel_dsi->ports) { in intel_dsi_prepare()
1387 intel_de_write(display, MIPI_DSI_FUNC_PRG(display, port), val); in intel_dsi_prepare()
1397 * In non-burst mode, Value greater than one DPI frame time in in intel_dsi_prepare()
1407 intel_dsi->video_mode == BURST_MODE) { in intel_dsi_prepare()
1408 intel_de_write(display, MIPI_HS_TX_TIMEOUT(display, port), in intel_dsi_prepare()
1409 …txbyteclkhs(adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) +… in intel_dsi_prepare()
1411 intel_de_write(display, MIPI_HS_TX_TIMEOUT(display, port), in intel_dsi_prepare()
1412 …txbyteclkhs(adjusted_mode->crtc_vtotal * adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, i… in intel_dsi_prepare()
1414 intel_de_write(display, MIPI_LP_RX_TIMEOUT(display, port), in intel_dsi_prepare()
1415 intel_dsi->lp_rx_timeout); in intel_dsi_prepare()
1416 intel_de_write(display, MIPI_TURN_AROUND_TIMEOUT(display, port), in intel_dsi_prepare()
1417 intel_dsi->turn_arnd_val); in intel_dsi_prepare()
1418 intel_de_write(display, MIPI_DEVICE_RESET_TIMER(display, port), in intel_dsi_prepare()
1419 intel_dsi->rst_timer_val); in intel_dsi_prepare()
1424 intel_de_write(display, MIPI_INIT_COUNT(display, port), in intel_dsi_prepare()
1425 txclkesc(intel_dsi->escape_clk_div, 100)); in intel_dsi_prepare()
1428 !intel_dsi->dual_link) { in intel_dsi_prepare()
1435 intel_de_write(display, in intel_dsi_prepare()
1436 MIPI_INIT_COUNT(display, port == PORT_A ? PORT_C : PORT_A), in intel_dsi_prepare()
1437 intel_dsi->init_count); in intel_dsi_prepare()
1441 intel_de_write(display, MIPI_EOT_DISABLE(display, port), tmp); in intel_dsi_prepare()
1444 intel_de_write(display, MIPI_INIT_COUNT(display, port), in intel_dsi_prepare()
1445 intel_dsi->init_count); in intel_dsi_prepare()
1452 intel_de_write(display, MIPI_HIGH_LOW_SWITCH_COUNT(display, port), in intel_dsi_prepare()
1453 intel_dsi->hs_to_lp_count); in intel_dsi_prepare()
1461 intel_de_write(display, MIPI_LP_BYTECLK(display, port), in intel_dsi_prepare()
1462 intel_dsi->lp_byte_clk); in intel_dsi_prepare()
1465 intel_de_write(display, MIPI_TLPX_TIME_COUNT(display, port), in intel_dsi_prepare()
1466 intel_dsi->lp_byte_clk); in intel_dsi_prepare()
1468 intel_de_write(display, MIPI_CLK_LANE_TIMING(display, port), in intel_dsi_prepare()
1469 intel_dsi->dphy_reg); in intel_dsi_prepare()
1476 * transmit 16 long packets in a dsi stream varies. */ in intel_dsi_prepare()
1477 intel_de_write(display, MIPI_DBI_BW_CTRL(display, port), in intel_dsi_prepare()
1478 intel_dsi->bw_timer); in intel_dsi_prepare()
1480 intel_de_write(display, MIPI_CLK_LANE_SWITCH_TIME_CNT(display, port), in intel_dsi_prepare()
1481 …intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_… in intel_dsi_prepare()
1484 u32 fmt = intel_dsi->video_frmt_cfg_bits | IP_TG_CONFIG; in intel_dsi_prepare()
1487 * Some panels might have resolution which is not a in intel_dsi_prepare()
1493 switch (intel_dsi->video_mode) { in intel_dsi_prepare()
1495 MISSING_CASE(intel_dsi->video_mode); in intel_dsi_prepare()
1508 intel_de_write(display, MIPI_VIDEO_MODE_FORMAT(display, port), fmt); in intel_dsi_prepare()
1515 struct intel_display *display = to_intel_display(encoder); in intel_dsi_unprepare() local
1516 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_unprepare()
1523 for_each_dsi_port(port, intel_dsi->ports) { in intel_dsi_unprepare()
1525 intel_de_write(display, MIPI_DEVICE_READY(display, port), 0x0); in intel_dsi_unprepare()
1531 intel_de_write(display, MIPI_EOT_DISABLE(display, port), CLOCKSTOP); in intel_dsi_unprepare()
1533 intel_de_rmw(display, MIPI_DSI_FUNC_PRG(display, port), VID_MODE_FORMAT_MASK, 0); in intel_dsi_unprepare()
1535 intel_de_write(display, MIPI_DEVICE_READY(display, port), 0x1); in intel_dsi_unprepare()
1546 struct drm_i915_private *i915 = to_i915(connector->dev); in vlv_dsi_mode_valid()
1582 intel_attach_scaling_mode_property(&connector->base); in vlv_dsi_add_properties()
1584 drm_connector_set_panel_orientation_with_quirk(&connector->base, in vlv_dsi_add_properties()
1586 fixed_mode->hdisplay, in vlv_dsi_add_properties()
1587 fixed_mode->vdisplay); in vlv_dsi_add_properties()
1599 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); in vlv_dphy_param_init()
1600 struct intel_connector *connector = intel_dsi->attached_connector; in vlv_dphy_param_init()
1601 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config; in vlv_dphy_param_init()
1612 switch (intel_dsi->lane_count) { in vlv_dphy_param_init()
1630 tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero; in vlv_dphy_param_init()
1631 ths_prepare_hszero = mipi_config->ths_prepare_hszero; in vlv_dphy_param_init()
1637 intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num); in vlv_dphy_param_init()
1649 ths_prepare_ns = max(mipi_config->ths_prepare, in vlv_dphy_param_init()
1650 mipi_config->tclk_prepare); in vlv_dphy_param_init()
1656 drm_dbg_kms(&dev_priv->drm, "prepare count too high %u\n", in vlv_dphy_param_init()
1663 (ths_prepare_hszero - ths_prepare_ns) * ui_den, in vlv_dphy_param_init()
1677 drm_dbg_kms(&dev_priv->drm, "exit zero count too high %u\n", in vlv_dphy_param_init()
1684 (tclk_prepare_clkzero - ths_prepare_ns) in vlv_dphy_param_init()
1688 drm_dbg_kms(&dev_priv->drm, "clock zero count too high %u\n", in vlv_dphy_param_init()
1694 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail); in vlv_dphy_param_init()
1698 drm_dbg_kms(&dev_priv->drm, "trail count too high %u\n", in vlv_dphy_param_init()
1704 intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 | in vlv_dphy_param_init()
1711 * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count in vlv_dphy_param_init()
1725 hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8); in vlv_dphy_param_init()
1727 intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch); in vlv_dphy_param_init()
1728 intel_dsi->hs_to_lp_count += extra_byte_count; in vlv_dphy_param_init()
1731 /* LP -> HS for clock lanes in vlv_dphy_param_init()
1739 intel_dsi->clk_lp_to_hs_count = in vlv_dphy_param_init()
1745 intel_dsi->clk_lp_to_hs_count += extra_byte_count; in vlv_dphy_param_init()
1747 /* HS->LP for Clock Lanes in vlv_dphy_param_init()
1754 intel_dsi->clk_hs_to_lp_count = in vlv_dphy_param_init()
1757 intel_dsi->clk_hs_to_lp_count += extra_byte_count; in vlv_dphy_param_init()
1764 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in vlv_dsi_min_cdclk()
1790 * Vtotal is wrong on the Asus TF103C leading to the last line of the display
1791 * being shown as the first line. The factory installed Android has a hardcoded
1797 * https://gitlab.freedesktop.org/drm/intel/-/issues/9381
1803 intel_panel_preferred_fixed_mode(intel_dsi->attached_connector); in vlv_dsi_asus_tf103c_mode_fixup()
1805 if (fixed_mode->vtotal == 820) in vlv_dsi_asus_tf103c_mode_fixup()
1806 fixed_mode->vtotal -= 4; in vlv_dsi_asus_tf103c_mode_fixup()
1811 * 1. The I2C MIPI sequence elements reference bus 3. ACPI has I2C1 - I2C7
1812 * which under Linux become bus 0 - 6. And the MIPI sequence reference
1817 * devices the I2C bus-numbers used in the MIPI sequences do
1820 * 2. width_/height_mm contain a bogus 192mm x 120mm size. This is
1821 * especially a problem on the 8" 830 version which uses a 10:16
1824 * https://gitlab.freedesktop.org/drm/intel/-/issues/9379
1829 intel_panel_preferred_fixed_mode(intel_dsi->attached_connector); in vlv_dsi_lenovo_yoga_tab2_size_fixup()
1830 struct drm_display_info *info = &intel_dsi->attached_connector->base.display_info; in vlv_dsi_lenovo_yoga_tab2_size_fixup()
1832 intel_dsi->i2c_bus_num = 2; in vlv_dsi_lenovo_yoga_tab2_size_fixup()
1835 * The 10" 1050 uses a 1920x1200 landscape screen, where as the 8" 830 in vlv_dsi_lenovo_yoga_tab2_size_fixup()
1836 * uses a 1200x1920 portrait screen. in vlv_dsi_lenovo_yoga_tab2_size_fixup()
1838 if (fixed_mode->hdisplay == 1920) { in vlv_dsi_lenovo_yoga_tab2_size_fixup()
1839 info->width_mm = 216; in vlv_dsi_lenovo_yoga_tab2_size_fixup()
1840 info->height_mm = 135; in vlv_dsi_lenovo_yoga_tab2_size_fixup()
1842 info->width_mm = 107; in vlv_dsi_lenovo_yoga_tab2_size_fixup()
1843 info->height_mm = 171; in vlv_dsi_lenovo_yoga_tab2_size_fixup()
1848 * On the Lenovo Yoga Tab 3 Pro YT3-X90F there are 2 problems:
1852 * Add a backlight off sequence mirroring the existing backlight on sequence.
1854 * https://gitlab.freedesktop.org/drm/intel/-/issues/9380
1859 /* Header Seq-id 7, length after header 11 bytes */ in vlv_dsi_lenovo_yoga_tab3_backlight_fixup()
1861 /* MIPI_SEQ_ELEM_I2C bus 0 addr 0x2c reg 0x00 data-len 1 data 0x00 */ in vlv_dsi_lenovo_yoga_tab3_backlight_fixup()
1866 struct intel_connector *connector = intel_dsi->attached_connector; in vlv_dsi_lenovo_yoga_tab3_backlight_fixup()
1868 intel_dsi->i2c_bus_num = 0; in vlv_dsi_lenovo_yoga_tab3_backlight_fixup()
1869 connector->panel.vbt.dsi.sequence[MIPI_SEQ_BACKLIGHT_OFF] = backlight_off_sequence; in vlv_dsi_lenovo_yoga_tab3_backlight_fixup()
1889 DMI_MATCH(DMI_BOARD_NAME, "BYT-T FFD8"),
1896 /* Lenovo Yoga Tab 3 Pro YT3-X90F */
1899 DMI_MATCH(DMI_PRODUCT_VERSION, "Blade3-10A-001"),
1908 struct intel_display *display = &dev_priv->display; in vlv_dsi_init() local
1917 drm_dbg_kms(&dev_priv->drm, "\n"); in vlv_dsi_init()
1920 if (!intel_bios_is_dsi_present(display, &port)) in vlv_dsi_init()
1924 dev_priv->display.dsi.mmio_base = BXT_MIPI_BASE; in vlv_dsi_init()
1926 dev_priv->display.dsi.mmio_base = VLV_MIPI_BASE; in vlv_dsi_init()
1938 encoder = &intel_dsi->base; in vlv_dsi_init()
1939 intel_dsi->attached_connector = connector; in vlv_dsi_init()
1941 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_dsi_funcs, in vlv_dsi_init()
1944 encoder->compute_config = intel_dsi_compute_config; in vlv_dsi_init()
1945 encoder->pre_enable = intel_dsi_pre_enable; in vlv_dsi_init()
1947 encoder->enable = bxt_dsi_enable; in vlv_dsi_init()
1948 encoder->disable = intel_dsi_disable; in vlv_dsi_init()
1949 encoder->post_disable = intel_dsi_post_disable; in vlv_dsi_init()
1950 encoder->get_hw_state = intel_dsi_get_hw_state; in vlv_dsi_init()
1951 encoder->get_config = intel_dsi_get_config; in vlv_dsi_init()
1952 encoder->update_pipe = intel_backlight_update; in vlv_dsi_init()
1953 encoder->shutdown = intel_dsi_shutdown; in vlv_dsi_init()
1955 connector->get_hw_state = intel_connector_get_hw_state; in vlv_dsi_init()
1957 encoder->port = port; in vlv_dsi_init()
1958 encoder->type = INTEL_OUTPUT_DSI; in vlv_dsi_init()
1959 encoder->power_domain = POWER_DOMAIN_PORT_DSI; in vlv_dsi_init()
1960 encoder->cloneable = 0; in vlv_dsi_init()
1963 * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI in vlv_dsi_init()
1967 encoder->pipe_mask = ~0; in vlv_dsi_init()
1969 encoder->pipe_mask = BIT(PIPE_A); in vlv_dsi_init()
1971 encoder->pipe_mask = BIT(PIPE_B); in vlv_dsi_init()
1973 intel_dsi->panel_power_off_time = ktime_get_boottime(); in vlv_dsi_init()
1975 intel_bios_init_panel_late(display, &connector->panel, NULL, NULL); in vlv_dsi_init()
1977 if (connector->panel.vbt.dsi.config->dual_link) in vlv_dsi_init()
1978 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C); in vlv_dsi_init()
1980 intel_dsi->ports = BIT(port); in vlv_dsi_init()
1982 if (drm_WARN_ON(&dev_priv->drm, connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports)) in vlv_dsi_init()
1983 connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports; in vlv_dsi_init()
1985 if (drm_WARN_ON(&dev_priv->drm, connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports)) in vlv_dsi_init()
1986 connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports; in vlv_dsi_init()
1988 /* Create a DSI host (and a device) for each port. */ in vlv_dsi_init()
1989 for_each_dsi_port(port, intel_dsi->ports) { in vlv_dsi_init()
1997 intel_dsi->dsi_hosts[port] = host; in vlv_dsi_init()
2001 drm_dbg_kms(&dev_priv->drm, "no device found\n"); in vlv_dsi_init()
2005 /* Use clock read-back from current hw-state for fastboot */ in vlv_dsi_init()
2008 drm_dbg_kms(&dev_priv->drm, "Calculated pclk %d GOP %d\n", in vlv_dsi_init()
2009 intel_dsi->pclk, current_mode->clock); in vlv_dsi_init()
2010 if (intel_fuzzy_clock_check(intel_dsi->pclk, in vlv_dsi_init()
2011 current_mode->clock)) { in vlv_dsi_init()
2012 drm_dbg_kms(&dev_priv->drm, "Using GOP pclk\n"); in vlv_dsi_init()
2013 intel_dsi->pclk = current_mode->clock; in vlv_dsi_init()
2024 drm_connector_init(&dev_priv->drm, &connector->base, &intel_dsi_connector_funcs, in vlv_dsi_init()
2027 drm_connector_helper_add(&connector->base, &intel_dsi_connector_helper_funcs); in vlv_dsi_init()
2029 connector->base.display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ in vlv_dsi_init()
2033 mutex_lock(&dev_priv->drm.mode_config.mutex); in vlv_dsi_init()
2035 mutex_unlock(&dev_priv->drm.mode_config.mutex); in vlv_dsi_init()
2038 drm_dbg_kms(&dev_priv->drm, "no fixed mode\n"); in vlv_dsi_init()
2045 (vlv_dsi_dmi_quirk_func)dmi_id->driver_data; in vlv_dsi_init()
2059 drm_connector_cleanup(&connector->base); in vlv_dsi_init()
2061 drm_encoder_cleanup(&encoder->base); in vlv_dsi_init()