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/linux-6.14.4/Documentation/devicetree/bindings/serial/
Dmvebu-uart.txt1 * Marvell UART : Non standard UART used in some of Marvell EBU SoCs
2 e.g., Armada-3700.
5 - compatible:
6 - "marvell,armada-3700-uart" for the standard variant of the UART
7 (32 bytes FIFO, no DMA, level interrupts, 8-bit access to the
9 - "marvell,armada-3700-uart-ext" for the extended variant of the
10 UART (128 bytes FIFO, DMA, front interrupts, 8-bit or 32-bit
12 - reg: offset and length of the register set for the device.
13 - clocks: UART reference clock used to derive the baudrate. If no clock
14 is provided (possible only with the "marvell,armada-3700-uart"
[all …]
Dst,stm32-uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/st,stm32-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 - Erwan Le Ray <[email protected]>
15 - st,stm32-uart
16 - st,stm32f7-uart
17 - st,stm32h7-uart
32 description: label associated with this uart
34 st,hw-flow-ctrl:
[all …]
Dfsl-imx-uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/fsl-imx-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX Universal Asynchronous Receiver/Transmitter (UART)
10 - Fabio Estevam <[email protected]>
15 - const: fsl,imx1-uart
16 - const: fsl,imx21-uart
17 - items:
18 - enum:
[all …]
Dingenic,uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/ingenic,uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ingenic SoCs UART controller
10 - Paul Cercueil <[email protected]>
13 - $ref: serial.yaml#
17 pattern: "^serial@[0-9a-f]+$"
21 - enum:
22 - ingenic,jz4740-uart
[all …]
Dserial.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <[email protected]>
11 - Greg Kroah-Hartman <[email protected]>
18 Each enabled UART may have an optional "serialN" alias in the "aliases" node,
19 where N is the port number (non-negative decimal integer) as printed on the
28 cts-gpios:
32 the UART's CTS line.
34 dcd-gpios:
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Dsamsung_uart.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S3C, S5P, Exynos, and S5L (Apple SoC) SoC UART Controller
10 - Krzysztof Kozlowski <[email protected]>
11 - Greg Kroah-Hartman <[email protected]>
14 Each Samsung UART should have an alias correctly numbered in the "aliases"
15 node, according to serialN format, where N is the port number (non-negative
21 - enum:
22 - apple,s5l-uart
[all …]
Dsprd-uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/serial/sprd-uart.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Spreadtrum serial UART
11 - Orson Zhai <[email protected]>
12 - Baolin Wang <[email protected]>
13 - Chunyan Zhang <[email protected]>
18 - items:
19 - enum:
[all …]
Dnvidia,tegra20-hsuart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/nvidia,tegra20-hsuart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra20/Tegra30 high speed (DMA based) UART controller driver
10 - Thierry Reding <[email protected]>
11 - Jon Hunter <[email protected]>
16 - enum:
17 - nvidia,tegra20-hsuart
18 - nvidia,tegra30-hsuart
[all …]
Dmediatek,uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/mediatek,uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek Universal Asynchronous Receiver/Transmitter (UART)
10 - Matthias Brugger <[email protected]>
13 - $ref: serial.yaml#
16 The MediaTek UART is based on the basic 8250 UART and compatible
23 - const: mediatek,mt6577-uart
24 - items:
[all …]
D8250.yaml3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UART (Universal Asynchronous Receiver/Transmitter)
10 - [email protected]
13 - $ref: serial.yaml#
14 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
15 - if:
17 - required:
18 - aspeed,lpc-io-reg
19 - required:
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D8250_omap.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vignesh Raghavendra <[email protected]>
13 - $ref: /schemas/serial/serial.yaml#
14 - $ref: /schemas/serial/rs485.yaml#
19 - enum:
20 - ti,am3352-uart
21 - ti,am4372-uart
22 - ti,am654-uart
[all …]
Dnvidia,tegra194-tcu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/serial/nvidia,tegra194-tcu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Combined UART (TCU)
10 - Thierry Reding <[email protected]>
11 - Jonathan Hunter <[email protected]>
14 The TCU is a system for sharing a hardware UART instance among multiple
15 systems within the Tegra SoC. It is implemented through a mailbox-
16 based protocol where each "virtual UART" has a pair of mailboxes, one
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/
Ducc.txt4 - device_type : should be "network", "hldc", "uart", "transparent"
6 - compatible : could be "ucc_geth" or "fsl_atm" and so on.
7 - cell-index : the ucc number(1-8), corresponding to UCCx in UM.
8 - reg : Offset and length of the register set for the device
9 - interrupts : <a b> where a is the interrupt number and b is a
14 - pio-handle : The phandle for the Parallel I/O port configuration.
15 - port-number : for UART drivers, the port number to use, between 0 and 3.
18 CPM UART driver, the port-number is required for the QE UART driver.
19 - soft-uart : for UART drivers, if specified this means the QE UART device
20 driver should use "Soft-UART" mode, which is needed on some SOCs that have
[all …]
/linux-6.14.4/drivers/tty/serial/
Darc_uart.c1 // SPDX-License-Identifier: GPL-2.0
3 * ARC On-Chip(fpga) UART Driver
5 * Copyright (C) 2010-2012 Synopsys, Inc. (www.synopsys.com)
8 * -Decoupled the driver from arch/arc
10 * +Using early_platform_xxx() for early console (thx to mach-shmobile/xxx)
13 * -Is uart_tx_stopped() not done in tty write path as it has already been
17 * -New Serial Core based ARC UART driver
18 * -Derived largely from blackfin driver albiet with some major tweaks
21 * -check if sysreq works
37 * ARC UART Hardware Specs
[all …]
Dsifive.c1 // SPDX-License-Identifier: GPL-2.0+
3 * SiFive UART driver
5 * Copyright (C) 2018-2019 SiFive
8 * - drivers/tty/serial/pxa.c
9 * - drivers/tty/serial/amba-pl011.c
10 * - drivers/tty/serial/uartlite.c
11 * - drivers/tty/serial/omap-serial.c
12 * - drivers/pwm/pwm-sifive.c
15 * - Chapter 19 "Universal Asynchronous Receiver/Transmitter (UART)" of
16 * SiFive FE310-G000 v2p3
[all …]
Dpic32_uart.c1 // SPDX-License-Identifier: GPL-2.0+
8 * Sorin-Andrei Pistirica <[email protected]>
26 #include <asm/mach-pic32/pic32.h>
28 /* UART name and device definitions */
29 #define PIC32_DEV_NAME "pic32-uart"
43 /* struct pic32_sport - pic32 serial port descriptor
44 * @port: uart port descriptor
50 * @irq_tx: virtual tx interrupt number
51 * @irq_tx_name: irq tx name
82 __raw_writel(val, sport->port.membase + reg); in pic32_uart_writel()
[all …]
Dmen_z135_uart.c1 // SPDX-License-Identifier: GPL-2.0
3 * MEN 16z135 High Speed UART
38 #define MEN_Z135_IER_TXCIEN BIT(1) /* TX Space IRQ */
104 MODULE_PARM_DESC(txlvl, "TX IRQ trigger level 0-7, default 5 (128 byte)");
108 MODULE_PARM_DESC(rxlvl, "RX IRQ trigger level 0-7, default 6 (256 byte)");
131 * men_z135_reg_set() - Set value in register
132 * @uart: The UART port
136 static inline void men_z135_reg_set(struct men_z135_port *uart, in men_z135_reg_set() argument
139 struct uart_port *port = &uart->port; in men_z135_reg_set()
143 spin_lock_irqsave(&uart->lock, flags); in men_z135_reg_set()
[all …]
Dtimbuart.c1 // SPDX-License-Identifier: GPL-2.0
3 * timbuart.c timberdale FPGA UART driver
8 * Timberdale FPGA UART
42 u32 ier = ioread32(port->membase + TIMBUART_IER) & ~RXFLAGS; in timbuart_stop_rx()
43 iowrite32(ier, port->membase + TIMBUART_IER); in timbuart_stop_rx()
48 /* spinlock held by upper layer, disable TX interrupt */ in timbuart_stop_tx()
49 u32 ier = ioread32(port->membase + TIMBUART_IER) & ~TXBAE; in timbuart_stop_tx()
50 iowrite32(ier, port->membase + TIMBUART_IER); in timbuart_stop_tx()
55 struct timbuart_port *uart = in timbuart_start_tx() local
58 /* do not transfer anything here -> fire off the tasklet */ in timbuart_start_tx()
[all …]
Dxilinx_uartps.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Cadence UART driver (found in Xilinx Zynq)
5 * Copyright (c) 2011 - 2014 Xilinx, Inc.
7 * This driver has originally been pushed by Xilinx using a Zynq-branding. This
42 MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
47 MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
49 /* Register offsets for the UART. */
67 #define CDNS_UART_TXWM 0x44 /* TX FIFO Trigger Level */
71 #define CDNS_UART_CR_STOPBRK 0x00000100 /* Stop TX break */
72 #define CDNS_UART_CR_STARTBRK 0x00000080 /* Set TX break */
[all …]
Dbcm63xx_uart.c1 // SPDX-License-Identifier: GPL-2.0
7 * Serial driver for BCM63xx integrated UART.
9 * Hardware flow control was _not_ tested since I only have RX/TX on
37 * - rx fifo full
38 * - rx fifo above threshold
39 * - rx fifo not empty for too long
50 * tx interrupt mask / stat
53 * - tx fifo empty
54 * - tx fifo below threshold
71 * handy uart register accessor
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/powerpc/fsl/
Dmpc5121-psc.txt3 PSC in UART mode
4 ----------------
6 For PSC in UART mode the needed PSC serial devices
7 are specified by fsl,mpc5121-psc-uart nodes in the
8 fsl,mpc5121-immr SoC node. Additionally the PSC FIFO
9 Controller node fsl,mpc5121-psc-fifo is required there:
11 fsl,mpc512x-psc-uart nodes
12 --------------------------
15 - compatible : Should contain "fsl,<soc>-psc-uart" and "fsl,<soc>-psc"
17 - reg : Offset and length of the register set for the PSC device
[all …]
/linux-6.14.4/arch/arm/mach-s3c/
Dpl080.c1 // SPDX-License-Identifier: GPL-2.0
3 // Samsung's S3C64XX generic DMA support using amba-pl08x driver.
17 #include "regs-sys-s3c64xx.h"
21 return cd->min_signal; in pl08x_get_xfer_signal()
117 { "s3c6400-uart.0", "tx", &s3c64xx_dma0_info[0] },
118 { "s3c6400-uart.0", "rx", &s3c64xx_dma0_info[1] },
119 { "s3c6400-uart.1", "tx", &s3c64xx_dma0_info[2] },
120 { "s3c6400-uart.1", "rx", &s3c64xx_dma0_info[3] },
121 { "s3c6400-uart.2", "tx", &s3c64xx_dma0_info[4] },
122 { "s3c6400-uart.2", "rx", &s3c64xx_dma0_info[5] },
[all …]
/linux-6.14.4/arch/arm/boot/dts/nxp/imx/
Dimx6qdl-dhcom-drc02.dtsi1 // SPDX-License-Identifier: GPL-2.0+
8 stdout-path = "serial0:115200n8";
14 * pins SD3_DAT0 and SD3_DAT1 are muxed as can2 Tx and Rx. The signals for can2
15 * Tx and Rx are routed to the DHCOM UART1 rts/cts pins. Therefore the micro SD
26 * GPIO line, however the i.MX6 UART driver assumes RX happens
27 * during TX anyway and that it only controls drive enable DE
30 rs485-rx-en-hog {
31 gpio-hog;
33 line-name = "rs485-rx-en";
34 output-low;
[all …]
/linux-6.14.4/drivers/usb/serial/
Dwhiteheat.h1 /* SPDX-License-Identifier: GPL-2.0+ */
9 * Greg Kroah-Hartman ([email protected])
11 * See Documentation/usb/usb-serial.rst for more information on using this
29 #define WHITEHEAT_PURGE 9 /* clear the UART fifos */
34 #define WHITEHEAT_REPORT_TX_DONE 12 /* get the next TX done */
73 stop/start TX */
82 will stop/start TX */
84 will stop/start TX */
90 __le32 baud; /* any value 7 - 460800, firmware calculates
131 * Type DATA: 0x00 - 0xff
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
Duqe_serial.txt4 compatible : must be "fsl,<chip>-ucc-uart". For t1040, must be
5 "fsl,t1040-ucc-uart".
6 port-number : port number of UCC-UART
7 tx/rx-clock-name : should be "brg1"-"brg16" for internal clock source,
8 should be "clk1"-"clk28" for external clock source.
13 compatible = "fsl,t1040-ucc-uart";
14 port-number = <0>;
15 rx-clock-name = "brg2";
16 tx-clock-name = "brg2";

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