Searched full:ref_sel (Results 1 – 7 of 7) sorted by relevance
201 u8 ref_sel;735 u8 ref_sel; in ad7173_find_live_config()745 cfg->ref_sel == cfg_aux->ref_sel) in ad7173_find_live_config()781 config = FIELD_PREP(AD7173_SETUP_REF_SEL_MASK, cfg->ref_sel); in ad7173_load_config()1005 *val = ad7173_get_ref_voltage_milli(st, ch->cfg.ref_sel); in ad7173_read_raw()1012 *val = ad7173_get_ref_voltage_milli(st, ch->cfg.ref_sel); in ad7173_read_raw()1326 static int ad7173_validate_reference(struct ad7173_state *st, int ref_sel) in ad7173_validate_reference() argument1331 if (ref_sel == AD7173_SETUP_REF_SEL_INT_REF && !st->info->has_int_ref) in ad7173_validate_reference()1335 if (ref_sel == AD7173_SETUP_REF_SEL_EXT_REF2 && !st->info->has_ref2) in ad7173_validate_reference()1339 ret = ad7173_get_ref_voltage_milli(st, ref_sel); in ad7173_validate_reference()[all …]
236 u32 ref_sel; member612 u32 ref_sel; in ad4130_setup_info_eq()623 a->ref_sel != b->ref_sel || in ad4130_setup_info_eq()724 FIELD_PREP(AD4130_CONFIG_REF_SEL_MASK, setup_info->ref_sel) | in ad4130_write_slot_setup()1011 if (val == st->scale_tbls[setup_info->ref_sel][pga][0] && in ad4130_set_channel_pga()1012 val2 == st->scale_tbls[setup_info->ref_sel][pga][1]) in ad4130_set_channel_pga()1122 *val = st->scale_tbls[setup_info->ref_sel][setup_info->pga][0]; in ad4130_read_raw()1123 *val2 = st->scale_tbls[setup_info->ref_sel][setup_info->pga][1]; in ad4130_read_raw()1155 *vals = (int *)st->scale_tbls[setup_info->ref_sel]; in ad4130_read_avail()1156 *length = ARRAY_SIZE(st->scale_tbls[setup_info->ref_sel]) * 2; in ad4130_read_avail()[all …]
65 that clock signal is always available, its rate is specified by REF_SEL75 Frequency of the REFCLK signal as defined by REF_SEL pins. If not
144 u8 ref_sel; member
52 PDEBUG("reg0 CFG1 ref_sel %d hibernate %d rf_vco_reg_en %d"
271 ts->stmpe->ref_sel = val; in stmpe_ts_get_platform_info()
552 STMPE_REF_SEL(stmpe->ref_sel); in stmpe811_adc_common_init()1396 stmpe->ref_sel = val; in stmpe_probe()