| /linux-6.14.4/arch/powerpc/kernel/ |
| D | dt_cpu_ftrs.c | 70 u64 lpcr; member
80 mtspr(SPRN_LPCR, system_registers.lpcr); in __restore_cpu_cpufeatures()
128 * LPCR does not get cleared, to match behaviour with secondaries in cpufeatures_setup_cpu()
130 * could clear LPCR too. in cpufeatures_setup_cpu()
211 u64 lpcr; in feat_enable_hv() local
221 lpcr = mfspr(SPRN_LPCR); in feat_enable_hv()
222 lpcr &= ~LPCR_LPES0; /* HV external interrupts */ in feat_enable_hv()
223 mtspr(SPRN_LPCR, lpcr); in feat_enable_hv()
245 u64 lpcr; in feat_enable_idle_nap() local
248 lpcr = mfspr(SPRN_LPCR); in feat_enable_idle_nap()
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| D | cpu_setup_power.c | 29 static void init_LPCR_ISA300(u64 lpcr, u64 lpes) in init_LPCR_ISA300() argument
32 lpcr |= (lpes << LPCR_LPES_SH) & LPCR_LPES; in init_LPCR_ISA300()
33 lpcr |= LPCR_PECE0|LPCR_PECE1|LPCR_PECE2; in init_LPCR_ISA300()
34 lpcr |= (4ull << LPCR_DPFD_SH) & LPCR_DPFD; in init_LPCR_ISA300()
35 lpcr &= ~LPCR_HDICE; /* clear HDICE */ in init_LPCR_ISA300()
36 lpcr |= (4ull << LPCR_VC_SH); in init_LPCR_ISA300()
37 mtspr(SPRN_LPCR, lpcr); in init_LPCR_ISA300()
42 * Setup a sane LPCR:
43 * Called with initial LPCR and desired LPES 2-bit value
54 static void init_LPCR_ISA206(u64 lpcr, u64 lpes) in init_LPCR_ISA206() argument
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| D | setup_64.c | 276 unsigned long lpcr = mfspr(SPRN_LPCR); in cpu_ready_for_interrupts() local
277 unsigned long new_lpcr = lpcr; in cpu_ready_for_interrupts()
290 if (new_lpcr != lpcr) in cpu_ready_for_interrupts()
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| D | exceptions-64s.S | 202 * guest. PR KVM runs with LPCR[AIL]=0 which causes interrupts to always be
803 * Interrupt Location (AIL) bit set in the LPCR. However this does not
1609 * When running in HV mode, Linux sets up the LPCR[LPES] bit such that
1613 * On bare metal POWER9 and later, Linux sets the LPCR[HVICE] bit such that
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| /linux-6.14.4/arch/powerpc/kvm/ |
| D | book3s_hv.c | 514 pr_err("lpcr = %.16lx sdr1 = %.16lx last_inst = %.16lx\n", in kvmppc_dump_regs()
515 vcpu->arch.vcore->lpcr, vcpu->kvm->arch.sdr1, in kvmppc_dump_regs()
2139 * Enforce limits on guest LPCR values based on hardware availability,
2143 unsigned long kvmppc_filter_lpcr_hv(struct kvm *kvm, unsigned long lpcr) in kvmppc_filter_lpcr_hv() argument
2147 lpcr &= ~LPCR_TC; in kvmppc_filter_lpcr_hv()
2151 lpcr &= ~LPCR_AIL; in kvmppc_filter_lpcr_hv()
2152 if ((lpcr & LPCR_AIL) != LPCR_AIL_3) in kvmppc_filter_lpcr_hv()
2153 lpcr &= ~LPCR_AIL; /* LPCR[AIL]=1/2 is disallowed */ in kvmppc_filter_lpcr_hv()
2161 lpcr &= ~LPCR_AIL; in kvmppc_filter_lpcr_hv()
2168 lpcr &= ~LPCR_LD; in kvmppc_filter_lpcr_hv()
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| D | book3s_hv_builtin.c | 539 * Perform MSR and PC adjustment for LPCR[AIL]=3 if it is set and in inject_interrupt()
547 (vcpu->arch.vcore->lpcr & LPCR_AIL) == LPCR_AIL_3 && in inject_interrupt()
573 unsigned long lpcr; in kvmppc_guest_entry_inject_int() local
577 /* Insert EXTERNAL bit into LPCR at the MER bit position */ in kvmppc_guest_entry_inject_int()
579 lpcr = mfspr(SPRN_LPCR); in kvmppc_guest_entry_inject_int()
580 lpcr |= ext << LPCR_MER_SH; in kvmppc_guest_entry_inject_int()
581 mtspr(SPRN_LPCR, lpcr); in kvmppc_guest_entry_inject_int()
589 if (!(lpcr & LPCR_LD)) in kvmppc_guest_entry_inject_int()
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| D | book3s_hv_p9_entry.c | 301 static void switch_mmu_to_guest_radix(struct kvm *kvm, struct kvm_vcpu *vcpu, u64 lpcr) in switch_mmu_to_guest_radix() argument
318 mtspr(SPRN_LPCR, lpcr); in switch_mmu_to_guest_radix()
326 static void switch_mmu_to_guest_hpt(struct kvm *kvm, struct kvm_vcpu *vcpu, u64 lpcr) in switch_mmu_to_guest_hpt() argument
343 mtspr(SPRN_LPCR, lpcr); in switch_mmu_to_guest_hpt()
356 u64 lpcr = kvm->arch.host_lpcr; in switch_mmu_to_host() local
368 mtspr(SPRN_LPCR, lpcr); in switch_mmu_to_host()
532 int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpcr, u64 *tb) in kvmhv_vcpu_entry_p9() argument
698 switch_mmu_to_guest_radix(kvm, vcpu, lpcr); in kvmhv_vcpu_entry_p9()
700 switch_mmu_to_guest_hpt(kvm, vcpu, lpcr); in kvmhv_vcpu_entry_p9()
706 * P9 suppresses the HDEC exception when LPCR[HDICE] = 0, in kvmhv_vcpu_entry_p9()
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| D | book3s_hv_nested.c | 72 hr->lpcr = swab64(hr->lpcr); in byteswap_hv_regs()
261 const struct hv_guest_state *l1_hv, u64 *lpcr) in load_l2_hv_regs() argument
269 * Don't let L1 change LPCR bits for the L2 except these: in load_l2_hv_regs()
277 *lpcr = kvmppc_filter_lpcr_hv(vcpu->kvm, in load_l2_hv_regs()
278 (vc->lpcr & ~mask) | (*lpcr & mask)); in load_l2_hv_regs()
303 u64 hdec_exp, lpcr; in kvmhv_enter_nested_guest() local
378 lpcr = l2_hv.lpcr; in kvmhv_enter_nested_guest()
379 load_l2_hv_regs(vcpu, &l2_hv, &saved_l1_hv, &lpcr); in kvmhv_enter_nested_guest()
384 r = kvmhv_run_single_vcpu(vcpu, hdec_exp, lpcr); in kvmhv_enter_nested_guest()
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| D | book3s_hv_interrupts.S | 63 * we need to set LPCR[HDICE] before writing HDEC.
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| D | book3s_hv_nestedv2.c | 329 vcpu->arch.vcore->lpcr); in gs_msg_ops_vcpu_fill_info()
574 vcpu->arch.vcore->lpcr = kvmppc_gse_get_u64(gse); in gs_msg_ops_vcpu_refresh_info()
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| D | book3s_hv_rmhandlers.S | 110 * we reloaded the host's LPCR value.
162 /* Set LPCR. */
817 /* Set LPCR. */
2173 * occurs, with PECE1 and PECE0 set in LPCR.
2190 kvm_nap_sequence: /* desired LPCR value in r5 */
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| D | book3s_64_mmu_hv.c | 1880 unsigned long senc, lpcr; in kvm_htab_write() local
1886 lpcr = senc << (LPCR_VRMASD_SH - 4); in kvm_htab_write()
1887 kvmppc_update_lpcr(kvm, lpcr, in kvm_htab_write()
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| /linux-6.14.4/drivers/gpu/drm/imx/lcdc/ |
| D | imx-lcdc.c | 71 /* Values for LPCR Register */
145 u32 lpcr, lvcr, lhcr; in imx_lcdc_update_hw_registers() local
177 lpcr = readl(lcdc->base + IMX21LCDC_LPCR); in imx_lcdc_update_hw_registers()
178 lpcr &= ~IMX21LCDC_LPCR_BPIX; in imx_lcdc_update_hw_registers()
179 lpcr |= FIELD_PREP(IMX21LCDC_LPCR_BPIX, imx_lcdc_get_format(fb->format->format)); in imx_lcdc_update_hw_registers()
180 writel(lpcr, lcdc->base + IMX21LCDC_LPCR); in imx_lcdc_update_hw_registers()
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| /linux-6.14.4/arch/powerpc/platforms/powernv/ |
| D | smp.c | 208 * offline, so clear LPCR:PECE1. We keep PECE2 (and in pnv_cpu_offline_self()
212 * the SLW engine sets LPCR with decrementer bit cleared, else in pnv_cpu_offline_self()
287 * Re-enable decrementer interrupts in LPCR. in pnv_cpu_offline_self()
290 * for non-hotplug cases. So program the LPCR via stop api as in pnv_cpu_offline_self()
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| D | idle.c | 70 * hid0, hid1, hid4, hid5, hmeer and lpcr values are symmetric across in pnv_save_sprs_for_deep_states()
299 u64 lpcr; member
349 sprs.lpcr = mfspr(SPRN_LPCR); in power7_idle_insn()
483 mtspr(SPRN_LPCR, sprs.lpcr); in power7_idle_insn()
587 u64 lpcr; member
664 sprs.lpcr = mfspr(SPRN_LPCR); in power9_idle_stop()
780 mtspr(SPRN_LPCR, sprs.lpcr); in power9_idle_stop()
1047 * Program the LPCR via stop-api only if the deepest stop state in pnv_program_cpu_hotplug_lpcr()
1117 * 1 - Exit from power-save mode controlled by LPCR's PECE bits
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| D | ocxl.c | 487 uint64_t lpcr, void __iomem **arva) in pnv_ocxl_map_lpar() argument
509 lparid, lpcr); in pnv_ocxl_map_lpar()
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| D | vas-window.c | 276 u64 lpcr, val; in init_xlate_regs() local
291 lpcr = mfspr(SPRN_LPCR); in init_xlate_regs()
301 val = SET_FIELD(VAS_XLATE_LPCR_ISL, val, lpcr & LPCR_ISL); in init_xlate_regs()
302 val = SET_FIELD(VAS_XLATE_LPCR_TC, val, lpcr & LPCR_TC); in init_xlate_regs()
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| /linux-6.14.4/drivers/rtc/ |
| D | rtc-snvs.c | 137 u32 lpcr; in snvs_rtc_enable() local
143 regmap_read(data->regmap, data->offset + SNVS_LPCR, &lpcr); in snvs_rtc_enable()
146 if (lpcr & SNVS_LPCR_SRTC_ENV) in snvs_rtc_enable()
149 if (!(lpcr & SNVS_LPCR_SRTC_ENV)) in snvs_rtc_enable()
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| /linux-6.14.4/arch/powerpc/mm/book3s64/ |
| D | radix_pgtable.c | 596 unsigned long lpcr; in radix__early_init_mmu() local
642 lpcr = mfspr(SPRN_LPCR); in radix__early_init_mmu()
643 mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR); in radix__early_init_mmu()
658 unsigned long lpcr; in radix__early_init_mmu_secondary() local
663 lpcr = mfspr(SPRN_LPCR); in radix__early_init_mmu_secondary()
664 mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR); in radix__early_init_mmu_secondary()
680 unsigned long lpcr; in radix__mmu_cleanup_all() local
683 lpcr = mfspr(SPRN_LPCR); in radix__mmu_cleanup_all()
684 mtspr(SPRN_LPCR, lpcr & ~LPCR_UPRT); in radix__mmu_cleanup_all()
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| /linux-6.14.4/arch/powerpc/include/asm/ |
| D | kvm_book3s.h | 90 ulong lpcr; member
263 unsigned long lpcr);
264 extern void kvmppc_update_lpcr(struct kvm *kvm, unsigned long lpcr,
314 u64 time_limit, unsigned long lpcr);
599 KVMPPC_BOOK3S_VCORE_ACCESSOR_GET(lpcr, 64, KVMPPC_GSID_LPCR)
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| D | pnv-ocxl.h | 79 uint64_t lpcr, void __iomem **arva);
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| D | opal.h | 32 uint64_t lpcr);
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| D | kvm_host.h | 289 unsigned long lpcr; member
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| /linux-6.14.4/Documentation/devicetree/bindings/crypto/ |
| D | fsl,sec-v4.0-mon.yaml | 125 SNVS_LP LPCR register.
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| /linux-6.14.4/tools/testing/selftests/powerpc/nx-gzip/include/ |
| D | nxu.h | 167 * translation information, such as MSR and LPCR bits, job
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