Searched full:lp0 (Results 1 – 25 of 32) sorted by relevance
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| /linux-6.14.4/Documentation/devicetree/bindings/soc/tegra/ |
| D | nvidia,tegra20-pmc.yaml | 80 - description: LP0, CPU + Core voltage off and DRAM in self-refresh
106 nvidia,lp0-vec:
109 Starting address and length of LP0 vector. The LP0 vector contains the
110 warm boot code that is executed by AVP when resuming from the LP0 state.
117 - description: starting address of LP0 vector
118 - description: length of LP0 vector
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| /linux-6.14.4/arch/arm/mach-tegra/ |
| D | sleep-tegra20.S | 140 * Enters suspend in LP0 or LP1 by turning off the mmu and jumping to
267 * puts memory in self-refresh for LP0 and LP1
277 * In LP0 and LP1 all PLLs will be turned off. Switch the CPU and system clock
323 * executes from IRAM with SDRAM in selfrefresh when target state is LP0 or LP1
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| D | sleep-tegra30.S | 37 #define PMC_CTRL_SIDE_EFFECT_LP0 (1 << 14) /* enter LP0 when CPU pwr gated */
281 * Enters suspend in LP0 or LP1 by turning off the MMU and jumping to
295 * LP0 / LP1 use physical address, since the MMU needs to be
648 * puts memory in self-refresh for LP0 and LP1
658 * In LP0 and LP1 all PLLs will be turned off. Switching the CPU and System CLK
745 * executes from IRAM with SDRAM in selfrefresh when target state is LP0 or LP1
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| D | pm.c | 261 * copy these code to IRAM before LP0/LP1 suspend and restore the content
343 [TEGRA_SUSPEND_LP0] = "LP0",
418 "self-refresh -- LP0/LP1 unavailable\n", in tegra_pm_init_suspend()
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| D | reset-handler.S | 29 * an LP2 transition. Also branched to by LP0 and LP1 resume after
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| /linux-6.14.4/Documentation/admin-guide/ |
| D | parport.rst | 221 Both the above examples would inform lp that you want ``/dev/lp0`` to be
226 name, so ``/dev/lp0`` was always the port at 0x3bc. This is no longer the
227 case - if you only have one port, it will default to being ``/dev/lp0``,
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| D | serial-console.rst | 25 lp0 for the first parallel port
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| D | devices.txt | 167 0 = /dev/lp0 Parallel printer on parport0
975 0 = /dev/pd_bdm0 PD BDM interface on lp0
978 4 = /dev/icd_bdm0 ICD BDM interface on lp0
2454 0 = /dev/usb/lp0 First USB printer
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| /linux-6.14.4/arch/arm/include/asm/mach/ |
| D | arch.h | 40 unsigned char reserve_lp0 :1; /* never has lp0 */
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| /linux-6.14.4/drivers/char/ |
| D | lp.c | 44 * lp=parport1,none,parport2 (bind lp0 to parport1, disable lp1 and
71 * lp0 0x3bc
77 * to lp0 regardless of its I/O address. If you need the old behaviour, you
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| D | Kconfig | 68 option "console=lp0" to the kernel at boot time.
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| /linux-6.14.4/arch/arm/kernel/ |
| D | setup.c | 209 #define lp0 io_res[0] macro
915 * possessing lp0, lp1 or lp2 in request_standard_resources()
918 request_resource(&ioport_resource, &lp0); in request_standard_resources()
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| /linux-6.14.4/arch/arm64/boot/dts/freescale/ |
| D | imx8mm-emtop-baseboard.dts | 362 MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 /* LP0: 32KHz */
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| /linux-6.14.4/drivers/gpu/drm/i915/display/ |
| D | i9xx_wm.c | 2677 * and thus fail gracefully if LP0 watermarks in ilk_validate_wm_level()
2777 /* ILK primary LP0 latency is 700 ns */ in ilk_read_wm_latency()
2786 /* ILK sprite LP0 latency is 1300 ns */ in intel_fixup_spr_wm_latency()
2794 /* ILK cursor LP0 latency is 1300 ns */ in intel_fixup_cur_wm_latency()
2895 /* LP0 watermark maximums depend on this pipe alone */ in ilk_validate_pipe_wm()
2903 /* LP0 watermarks always use 1/2 DDB partitioning */ in ilk_validate_pipe_wm()
2906 /* At least LP0 must be valid */ in ilk_validate_pipe_wm()
2908 drm_dbg_kms(&dev_priv->drm, "LP0 watermark invalid\n"); in ilk_validate_pipe_wm()
3218 /* LP0 register values */ in ilk_compute_wm_results()
3509 * For active pipes LP0 watermark is marked as in ilk_pipe_wm_get_hw_state()
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| D | intel_atomic_plane.c | 484 * down to LP0 and wait for vblank in order to make sure the in ilk_must_disable_cxsr()
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| /linux-6.14.4/drivers/soc/tegra/ |
| D | regulators-tegra30.c | 372 * hardware for resuming from LP0. in tegra30_regulator_prepare_suspend()
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| D | regulators-tegra20.c | 387 * hardware for resuming from LP0. in tegra20_regulator_prepare_suspend()
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| D | pmc.c | 67 #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */
374 * LP0 or SC7). Wakeup from other sleep states (such as LP1 or LP2)
411 * @lp0_vec_phys: physical base address of the LP0 warm boot code
412 * @lp0_vec_size: size of the LP0 warm boot code
1890 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values, in tegra_pmc_parse_dt()
3333 "LP0"
3690 "LP0",
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| /linux-6.14.4/Documentation/usb/ |
| D | gadget-testing.rst | 914 If udev is active, then e.g. /dev/usb/lp0 should appear.
924 # cat > /dev/usb/lp0
932 # cat /dev/usb/lp0
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| /linux-6.14.4/drivers/ata/ |
| D | ahci_tegra.c | 616 /* LP0 suspend support not implemented */
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| /linux-6.14.4/arch/arm/boot/dts/nvidia/ |
| D | tegra124-nyan.dtsi | 748 vdd_3v3_lp0: regulator-lp0 {
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| D | tegra124-venice2.dts | 1196 vdd_3v3_lp0: regulator-lp0 {
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| /linux-6.14.4/drivers/scsi/isci/ |
| D | port_config.c | 153 * hardware. The SCU hardware allows for port configurations as follows. LP0
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| /linux-6.14.4/arch/arm64/boot/dts/nvidia/ |
| D | tegra132-norrin.dts | 1182 vdd_3v3_lp0: regulator-vdd-3v3-lp0 {
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| /linux-6.14.4/drivers/interconnect/qcom/ |
| D | sm8750.c | 1252 .name = "LP0",
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