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/linux-6.14.4/Documentation/devicetree/bindings/phy/
Dphy-rockchip-naneng-combphy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,rk3568-naneng-combphy
16 - rockchip,rk3576-naneng-combphy
17 - rockchip,rk3588-naneng-combphy
24 - description: reference clock
25 - description: apb clock
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/linux-6.14.4/drivers/phy/xilinx/
Dphy-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5 * Copyright (C) 2018-2020 Xilinx Inc.
27 #include <dt-bindings/phy/phy.h>
33 /* TX De-emphasis parameters */
62 /* PLL SSC step size offsets */
71 /* SSC step size parameters */
184 * struct xpsgtr_ssc - structure to hold SSC settings for a lane
187 * @steps: number of steps of SSC (Spread Spectrum Clock)
198 * struct xpsgtr_phy - representation of a lane
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/linux-6.14.4/drivers/clk/
Dclk-renesas-pcie.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Driver for Renesas 9-series PCIe clock generator driver
6 * - 9FGV/9DBV/9DMV/9FGL/9DML/9QXL/9SQ
8 * - 9FGV0241
9 * - 9FGV0441
10 * - 9FGV0841
12 * Copyright (C) 2022 Marek Vasut <marex@denx.de>
15 #include <linux/clk-provider.h>
56 /* Structure to describe features of a particular 9-series model */
74 * Renesas 9-series i2c regmap
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/linux-6.14.4/drivers/gpu/drm/i915/display/
Dintel_pch_refclk.c1 // SPDX-License-Identifier: MIT
20 drm_err(&dev_priv->drm, "FDI mPHY reset assert timeout\n"); in lpt_fdi_reset_mphy()
26 drm_err(&dev_priv->drm, "FDI mPHY reset de-assert timeout\n"); in lpt_fdi_reset_mphy()
131 p->iclk_virtual_root_freq = 172800 * 1000; in iclkip_params_init()
132 p->iclk_pi_range = 64; in iclkip_params_init()
137 return DIV_ROUND_CLOSEST(p->iclk_virtual_root_freq, in lpt_iclkip_freq()
138 p->desired_divisor << p->auxdiv); in lpt_iclkip_freq()
146 * but the adjusted_mode->crtc_clock in KHz. To get the in lpt_compute_iclkip()
151 for (p->auxdiv = 0; p->auxdiv < 2; p->auxdiv++) { in lpt_compute_iclkip()
152 p->desired_divisor = DIV_ROUND_CLOSEST(p->iclk_virtual_root_freq, in lpt_compute_iclkip()
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Dintel_display_power.c1 /* SPDX-License-Identifier: MIT */
33 for_each_if(test_bit((__domain), (__power_well)->domains.bits))
37 for_each_if(test_bit((__domain), (__power_well)->domains.bits))
207 if (pm_runtime_suspended(display->drm->dev)) in __intel_display_power_is_enabled()
226 * intel_display_power_is_enabled - check for a power domain
245 struct intel_display *display = &dev_priv->display; in intel_display_power_is_enabled()
246 struct i915_power_domains *power_domains = &display->power.domains; in intel_display_power_is_enabled()
249 mutex_lock(&power_domains->lock); in intel_display_power_is_enabled()
251 mutex_unlock(&power_domains->lock); in intel_display_power_is_enabled()
260 struct i915_power_domains *power_domains = &display->power.domains; in sanitize_target_dc_state()
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/linux-6.14.4/drivers/phy/st/
Dphy-miphy28lp.c1 // SPDX-License-Identifier: GPL-2.0-only
25 #include <dt-bindings/phy/phy.h>
171 * 0: 30MHz crystal clk - 1: 100MHz ext clk routed through MiPHY1
173 * 1: 30MHz crystal clk - 0: 100MHz ext clk routed through MiPHY1
211 bool ssc; member
233 static char *PHY_TYPE_name[] = { "sata-up", "pcie-up", "", "usb3-up" };
362 void __iomem *base = miphy_phy->base; in miphy28lp_set_reset()
373 /* Bringing the MIPHY-CPU registers out of reset */ in miphy28lp_set_reset()
374 if (miphy_phy->type == PHY_TYPE_PCIE) { in miphy28lp_set_reset()
386 void __iomem *base = miphy_phy->base; in miphy28lp_pll_calibration()
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/linux-6.14.4/Documentation/devicetree/bindings/display/bridge/
Dite,it6263.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <[email protected]>
13 The IT6263 is a high-performance single-chip De-SSC(De-Spread Spectrum) LVDS
16 The built-in LVDS receiver can support single-link and dual-link LVDS inputs,
17 and the built-in HDMI transmitter is fully compliant with HDMI 1.4a/3D, HDCP
24 The newly supported High-Bit Rate(HBR) audio by HDMI specifications v1.3 is
30 - $ref: /schemas/display/lvds-dual-ports.yaml#
43 clock-names:
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/linux-6.14.4/drivers/phy/cadence/
Dphy-cadence-torrent.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/phy/phy-cadence.h>
12 #include <linux/clk-provider.h>
239 [CDNS_TORRENT_REFCLK_DRIVER] = "refclk-driver",
240 [CDNS_TORRENT_DERIVED_REFCLK] = "refclk-der",
241 [CDNS_TORRENT_RECEIVED_REFCLK] = "refclk-rec",
329 #define CDNS_TORRENT_KEY(refclk0, refclk1, link0, link1, ssc) \ argument
334 (((ssc) << SSC_SHIFT) & SSC_MASK))
463 enum cdns_torrent_ssc_mode ssc) in cdns_torrent_get_tbl_vals() argument
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/linux-6.14.4/drivers/spi/
Dspi-lantiq-ssc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011-2015 Daniel Schwierzeck <[email protected]>
4 * Copyright (C) 2016 Hauke Mehrtens <hauke@hauke-m.de>
142 #define LTQ_SPI_RXCNT_TODO_M 0xFFFF /* Receive to-do value */
191 return __raw_readl(spi->regbase + reg); in lantiq_ssc_readl()
197 __raw_writel(val, spi->regbase + reg); in lantiq_ssc_writel()
203 u32 val = __raw_readl(spi->regbase + reg); in lantiq_ssc_maskl()
207 __raw_writel(val, spi->regbase + reg); in lantiq_ssc_maskl()
212 const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg; in tx_fifo_level()
215 return (fstat >> LTQ_SPI_FSTAT_TXFFL_S) & hwcfg->fifo_size_mask; in tx_fifo_level()
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
13 dynamic device discovery; some are even write-only or read-only.
17 chips, analog to digital (and d-to-a) converters, and more.
44 If your system has an master-capable SPI controller (which
56 by providing a high-level interface to send memory-like commands.
66 This enables support for SPI-NAND mode on the Airoha NAND
68 is implemented as a SPI-MEM controller.
107 to a single device like spi-nor (nvram), input device controller
166 supports spi-mem interface.
245 this code to manage the per-word or per-transfer accesses to the
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/linux-6.14.4/drivers/pci/controller/
Dpcie-brcmstb.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2009 - 2019 Broadcom */
26 #include <linux/pci-ecam.h>
37 /* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
165 #define BRCM_INT_PCI_MSI_MASK GENMASK(BRCM_INT_PCI_MSI_NR - 1, 0)
167 32 - BRCM_INT_PCI_MSI_LEGACY_NR)
194 #define IDX_ADDR(pcie) ((pcie)->reg_offsets[EXT_CFG_INDEX])
195 #define DATA_ADDR(pcie) ((pcie)->reg_offsets[EXT_CFG_DATA])
196 #define PCIE_RGR1_SW_INIT_1(pcie) ((pcie)->reg_offsets[RGR1_SW_INIT_1])
197 #define HARD_DEBUG(pcie) ((pcie)->reg_offsets[PCIE_HARD_DEBUG])
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/linux-6.14.4/drivers/gpu/drm/msm/dsi/phy/
Ddsi_phy_14nm.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
17 * DSI PLL 14nm - clock diagram (eg: DSI0):
22 * +----+ | +----+
23 * dsi0vco_clk ---| n1 |--o--| /8 |-- dsi0pllbyte
24 * +----+ | +----+
26 * | +----+ |
27 * o---| /2 |--o--|\
28 * | +----+ | \ +----+
29 * | | |--| n2 |-- dsi0pll
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Ddsi_phy_10nm.c2 * SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
15 * DSI PLL 10nm - clock diagram (eg: DSI0):
20 * +---------+ | +----------+ | +----+
21 * dsi0vco_clk ---| out_div |--o--| divl_3_0 |--o--| /8 |-- dsi0_phy_pll_out_byteclk
22 * +---------+ | +----------+ | +----+
26 * | | +----+ | |\ dsi0_pclk_mux
27 * | |--| /2 |--o--| \ |
28 * | | +----+ | \ | +---------+
29 …* | --------------| |--o--| div_7_4 |-- dsi0_phy_pll_…
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Ddsi_phy_7nm.c2 * SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
15 * DSI PLL 7nm - clock diagram (eg: DSI0): TODO: updated CPHY diagram
20 * +---------+ | +----------+ | +----+
21 * dsi0vco_clk ---| out_div |--o--| divl_3_0 |--o--| /8 |-- dsi0_phy_pll_out_byteclk
22 * +---------+ | +----------+ | +----+
26 * | | +----+ | |\ dsi0_pclk_mux
27 * | |--| /2 |--o--| \ |
28 * | | +----+ | \ | +---------+
29 …* | --------------| |--o--| div_7_4 |-- dsi0_phy_pll_…
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/linux-6.14.4/drivers/phy/
Dphy-xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
22 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
23 * | | | | ---------
24 * External Clock ------| | -------------
25 * |------|
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/linux-6.14.4/drivers/phy/broadcom/
Dphy-brcm-usb-init.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * phy-brcm-usb-init.c - Broadcom USB Phy chip specific init functions
5 * Copyright (C) 2014-2017 Broadcom
16 #include "phy-brcm-usb-init.h"
142 (params->usb_reg_bits_map[USB_CTRL_##reg##_##field##_SELECTOR])
450 mask = params->usb_reg_bits_map[field]; in usb_ctrl_unset_family()
451 brcm_usb_ctrl_unset(params->regs[BRCM_REGS_CTRL] + reg_offset, mask); in usb_ctrl_unset_family()
460 mask = params->usb_reg_bits_map[field]; in usb_ctrl_set_family()
461 brcm_usb_ctrl_set(params->regs[BRCM_REGS_CTRL] + reg_offset, mask); in usb_ctrl_set_family()
534 /* Re-enable USB 3.0 pipe reset */ in brcmusb_usb3_enable_pipe_reset()
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/linux-6.14.4/
DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-[email protected]
88 F: drivers/scsi/3w-*
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/linux-6.14.4/drivers/gpu/drm/i915/
Di915_reg.h18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
44 * registers that are defined solely for the use by function-like macros.
52 * should be defined using function-like macros.
58 * with underscore, followed by a function-like macro choosing the right
68 * function-like macros may be used to define bit fields, but do note that the
87 * Try to re-use existing register macro definitions. Only add new macros for
232 * [0-7] @ 0x2000 gen2,gen3
233 * [8-15] @ 0x3000 945,g33,pnv
235 * [0-15] @ 0x3000 gen4,gen5
237 * [0-15] @ 0x100000 gen6,vlv,chv
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/linux-6.14.4/drivers/phy/mediatek/
Dphy-mtk-tphy.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/phy/phy.h>
15 #include <linux/nvmem-consumer.h>
22 #include "phy-mtk-io.h"
24 /* version V1 sub-banks offset base address */
35 /* version V2/V3 sub-banks offset base address */
220 /* CDR Charge Pump P-path current adjustment */
239 /* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */
248 /* I-path capacitance adjustment for Gen1 */
377 [U3P_EFUSE_TX_IMP] = "tx-imp",
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/linux-6.14.4/drivers/gpu/drm/amd/include/
Datombios.h2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
107 #define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication
108 #define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication
110 #define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV,…
222 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
245 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
427 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
433 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
440 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
538 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
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/linux-6.14.4/drivers/s390/block/
Ddasd_eckd.c1 // SPDX-License-Identifier: GPL-2.0
3 * Author(s)......: Holger Smolinski <Holger.Smolinski@de.ibm.com>
4 * Horst Hummel <Horst.Hummel@de.ibm.com>
5 * Carsten Otte <Cotte@de.ibm.com>
6 * Martin Schwidefsky <schwidefsky@de.ibm.com>
7 * Bugreports.to..: <Linux390@de.ibm.com>
134 /* set ECKD specific ccw-device options */ in dasd_eckd_probe()
140 "ccw-device options"); in dasd_eckd_probe()
163 return (d1 + (d2 - 1)) / d2; in ceil_quot()
172 switch (rdc->dev_type) { in recs_per_track()
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/linux-6.14.4/drivers/gpu/drm/xlnx/
Dzynqmp_dp.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2017 - 2020 Xilinx, Inc.
8 * - Hyun Woo Kwon <[email protected]>
9 * - Laurent Pinchart <[email protected]>
27 #include <linux/media-bus-format.h>
249 * struct zynqmp_dp_link_config - Common link config between source and sink
259 * struct zynqmp_dp_mode - Configured mode of DisplayPort
273 * struct zynqmp_dp_config - Configuration of DisplayPort from DTS
285 * enum test_pattern - Test patterns for test testing
289 * @TEST_80BIT_CUSTOM: A custom 80-bit pattern
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/linux-6.14.4/drivers/scsi/
Dst.c1 // SPDX-License-Identifier: GPL-2.0-only
13 Copyright 1992 - 2016 Kai Makisara
16 Some small formal changes - aeb, 950809
18 Last modified: 18-JAN-1998 Richard Gooch <[email protected]> Devfs support
62 is defined and non-zero. */
159 6-byte SCSI read and write commands. */
160 #if ST_FIXED_BUFFER_SIZE >= (2 << 24 - 1)
161 #error "Buffer size should not exceed (2 << 24 - 1) bytes!"
174 /* Remove mode bits and auto-rewind bit (7) */
176 (iminor(x) & ((1 << ST_MODE_SHIFT)-1)))
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/linux-6.14.4/drivers/net/ethernet/intel/e1000e/
Dich8lan.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
5 * 82562G-2 10/100 Network Connection
7 * 82562GT-2 10/100 Network Connection
9 * 82562V-2 10/100 Network Connection
10 * 82566DC-2 Gigabit Network Connection
12 * 82566DM-2 Gigabit Network Connection
19 * 82567LM-2 Gigabit Network Connection
20 * 82567LF-2 Gigabit Network Connection
21 * 82567V-2 Gigabit Network Connection
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