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/linux-6.14.4/Documentation/devicetree/bindings/ptp/
Dbrcm,ptp-dte.txt1 * Broadcom Digital Timing Engine(DTE) based PTP clock
9 "brcm,ptp-dte"
11 "brcm,iproc-ptp-dte" - for iproc based SoC's
12 - reg: address and length of the DTE block's NCO registers
16 ptp: ptp-dte@180af650 {
17 compatible = "brcm,iproc-ptp-dte", "brcm,ptp-dte";
/linux-6.14.4/drivers/iommu/
Drockchip-iommu.c101 phys_addr_t (*pt_address)(u32 dte);
162 * | DTE | -> +-----+
176 * Each DTE has a PT address and a valid bit:
187 static inline phys_addr_t rk_dte_pt_address(u32 dte) in rk_dte_pt_address() argument
189 return (phys_addr_t)dte & RK_DTE_PT_ADDRESS_MASK; in rk_dte_pt_address()
208 static inline phys_addr_t rk_dte_pt_address_v2(u32 dte) in rk_dte_pt_address_v2() argument
210 u64 dte_v2 = dte; in rk_dte_pt_address_v2()
219 static inline bool rk_dte_is_pt_valid(u32 dte) in rk_dte_is_pt_valid() argument
221 return dte & RK_DTE_PT_VALID; in rk_dte_is_pt_valid()
309 * | DTE index | PTE index | Page offset |
[all …]
Dsun50i-iommu.c152 * 4096 4-bytes Directory Table Entries (DTE), each pointing to a Page
197 static phys_addr_t sun50i_dte_get_pt_address(u32 dte) in sun50i_dte_get_pt_address() argument
199 return (phys_addr_t)dte & SUN50I_DTE_PT_ADDRESS_MASK; in sun50i_dte_get_pt_address()
202 static bool sun50i_dte_is_pt_valid(u32 dte) in sun50i_dte_is_pt_valid() argument
204 return (dte & SUN50I_DTE_PT_ATTRS) == SUN50I_DTE_PT_VALID; in sun50i_dte_is_pt_valid()
563 u32 dte; in sun50i_dte_get_page_table() local
566 dte = *dte_addr; in sun50i_dte_get_page_table()
567 if (sun50i_dte_is_pt_valid(dte)) { in sun50i_dte_get_page_table()
568 phys_addr_t pt_phys = sun50i_dte_get_pt_address(dte); in sun50i_dte_get_page_table()
576 dte = sun50i_mk_dte(virt_to_phys(page_table)); in sun50i_dte_get_page_table()
[all …]
/linux-6.14.4/drivers/i2c/busses/
Di2c-sh_mobile.c32 /* IRQ: DTE WAIT */
39 /* IRQ: DTE WAIT WAIT */
40 /* ICIC: -DTE */
46 /* IRQ: DTE WAIT WAIT WAIT */
47 /* ICIC: -DTE */
60 /* IRQ: DTE WAIT | WAIT DTE */
61 /* ICIC: -DTE | +DTE */
67 /* IRQ: DTE WAIT | WAIT WAIT DTE */
68 /* ICIC: -DTE | +DTE */
74 /* IRQ: DTE WAIT | WAIT WAIT WAIT DTE */
[all …]
/linux-6.14.4/net/x25/
Dx25_facilities.c32 * @dte_facs: ITU DTE facilities, updated as DTE facilities are found
266 struct x25_facilities *new, struct x25_dte_facilities *dte) in x25_negotiate_facilities() argument
275 memset(dte, 0, sizeof(*dte)); in x25_negotiate_facilities()
277 len = x25_parse_facilities(skb, &theirs, dte, &x25->vc_facil_mask); in x25_negotiate_facilities()
/linux-6.14.4/drivers/ptp/
Dptp_dte.c40 /* ptp dte priv structure */
218 .name = "DTE PTP timer",
318 { .compatible = "brcm,ptp-dte", },
325 .name = "ptp-dte",
335 MODULE_DESCRIPTION("Broadcom DTE PTP Clock driver");
DKconfig43 tristate "Broadcom DTE as PTP clock"
50 (DTE) in the Broadcom SoC's as a PTP clock.
/linux-6.14.4/drivers/iommu/amd/
Diommu.c101 * - Need cmpxchg16b instruction mainly for 128-bit store to DTE in amd_iommu_atomic128_set()
103 * protected by a spin_lock for this DTE). in amd_iommu_atomic128_set()
133 * but the driver is programming DTE using 2 128-bit cmpxchg. So, the driver
135 * - DTE[V|GV] bit is being written last when setting.
136 * - DTE[V|GV] bit is being written first when clearing.
138 * This function is used only by code, which updates DMA translation part of the DTE.
151 /* Existing DTE is not valid. */ in update_dte256()
156 /* Existing DTE is valid. New DTE is not valid. */ in update_dte256()
163 * Existing DTE has no guest page table. in update_dte256()
171 * Existing DTE has guest page table, in update_dte256()
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Dinit.c987 static void set_dte_bit(struct dev_table_entry *dte, u8 bit) in set_dte_bit() argument
992 dte->data[i] |= (1UL << _bit); in set_dte_bit()
1117 struct dev_table_entry *dte = NULL; in amd_iommu_get_ivhd_dte_flags() local
1129 dte = &(e->dte); in amd_iommu_get_ivhd_dte_flags()
1134 return dte; in amd_iommu_get_ivhd_dte_flags()
1159 struct dev_table_entry dte = {}; in set_dev_entry_from_acpi_range() local
1161 /* Parse IVHD DTE setting flags and store information */ in set_dev_entry_from_acpi_range()
1175 set_dte_bit(&dte, DEV_ENTRY_INIT_PASS); in set_dev_entry_from_acpi_range()
1177 set_dte_bit(&dte, DEV_ENTRY_EINT_PASS); in set_dev_entry_from_acpi_range()
1179 set_dte_bit(&dte, DEV_ENTRY_NMI_PASS); in set_dev_entry_from_acpi_range()
[all …]
Damd_iommu_types.h306 /* Bit value definition for dte irq remapping fields*/
406 * Bit value definition for DTE fields
430 /* DTE[128:179] | DTE[184:191] */
845 spinlock_t dte_lock; /* DTE lock for 256-bit access */
897 * Structure to sture persistent DTE flags from IVHD
904 struct dev_table_entry dte; member
/linux-6.14.4/Documentation/devicetree/bindings/serial/
Dfsl-imx-uart.yaml75 fsl,dte-mode:
78 Indicate the uart works in DTE mode. The uart works in DCE mode by default.
152 fsl,dte-mode;
/linux-6.14.4/Documentation/ABI/testing/
Dsysfs-class-led-trigger-tty29 DCE is ready to accept data from the DTE.
49 DTE is receiving a carrier from the DCE.
/linux-6.14.4/include/uapi/linux/
Dx25.h67 * DTE/DCE subscription options.
111 * ITU DTE facilities
Datmsap.h36 #define ATM_L2_ISO7776 0x11 /* ISO 7776 DTE-DTE */
/linux-6.14.4/arch/arm/boot/dts/nxp/imx/
Dimx6qdl-apalis.dtsi812 fsl,dte-mode;
820 fsl,dte-mode;
828 fsl,dte-mode;
835 fsl,dte-mode;
1276 /* DTE mode */
1293 /* DTE mode */
1310 /* DTE mode */
1325 /* DTE mode */
Dimx6dl-eckelmann-ci4x10.dts332 fsl,dte-mode;
343 fsl,dte-mode;
Dimx6ull-colibri.dtsi274 fsl,dte-mode;
282 fsl,dte-mode;
289 fsl,dte-mode;
Dimx6qdl-colibri.dtsi671 fsl,dte-mode;
680 fsl,dte-mode;
689 fsl,dte-mode;
1049 /* DTE mode */
Dmba6ulx.dtsi344 /* for DTE mode, add below change */
345 /* fsl,dte-mode; */
/linux-6.14.4/drivers/net/wan/
Dwanxl.c9 * - Only DTE (external clock) support with NRZ and NRZI encodings
112 const char *cable, *pm, *dte = "", *dsr = "", *dcd = ""; in wanxl_cable_intr() local
163 dte = (value & STATUS_CABLE_DCE) ? " DCE" : " DTE"; in wanxl_cable_intr()
166 pm, dte, cable, dsr, dcd); in wanxl_cable_intr()
/linux-6.14.4/Documentation/virt/kvm/devices/
Darm-vgic-its.rst156 Device Table Entry (DTE)::
166 corresponds to the DeviceID offset to the next DTE, capped by
/linux-6.14.4/Documentation/translations/zh_CN/security/
Dlsm.rst29 特定的访问控制模型(例如LIDS、DTE、SubDomain)。每个项目都开发并维护了自
/linux-6.14.4/include/uapi/linux/hdlc/
Dioctl.h9 #define CLOCK_EXT 1 /* External TX and RX clock - DTE */
/linux-6.14.4/arch/arm/boot/dts/nvidia/
Dtegra20-trimslice.dts98 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
213 "dte", "gma", "gmc", "gmd", "gpu",
Dtegra20-tamonten.dtsi92 nvidia,pins = "dtb", "dtc", "dte";
206 "dtc", "dte", "gpu", "sdio1",

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