101 	 * - Need cmpxchg16b instruction mainly for 128-bit store to DTE  in amd_iommu_atomic128_set()
103 	 *   protected by a spin_lock for this DTE).  in amd_iommu_atomic128_set()
133  * but the driver is programming DTE using 2 128-bit cmpxchg. So, the driver
135  *   - DTE[V|GV] bit is being written last when setting.
136  *   - DTE[V|GV] bit is being written first when clearing.
138  * This function is used only by code, which updates DMA translation part of the DTE.
151 		/* Existing DTE is not valid. */  in update_dte256()
156 		/* Existing DTE is valid. New DTE is not valid.  */  in update_dte256()
163 		 * Existing DTE has no guest page table.  in update_dte256()
171 		 * Existing DTE has guest page table,  in update_dte256()
172 		 * new DTE has no guest page table,  in update_dte256()
187 		/* First disable DTE */  in update_dte256()
191 		/* Then update DTE */  in update_dte256()
199 		 * update the lower 128-bit. So no need to disable DTE.  in update_dte256()
208 		      struct dev_table_entry *dte)  in get_dte256()  argument
217 	dte->data128[0] = ptr->data128[0];  in get_dte256()
218 	dte->data128[1] = ptr->data128[1];  in get_dte256()
725 	struct dev_table_entry dte;  in dump_dte_entry()  local
728 	get_dte256(iommu, dev_data, &dte);  in dump_dte_entry()
731 		pr_err("DTE[%d]: %016llx\n", i, dte.data[i]);  in dump_dte_entry()
1986 	/* All existing DTE must have V bit set */  in make_clear_dte()
2036 	struct dev_table_entry *dte = &get_dev_table(iommu)[dev_data->devid];  in set_dte_entry()  local
2043 	make_clear_dte(dev_data, dte, &new);  in set_dte_entry()
2070 	old_domid = READ_ONCE(dte->data[1]) & DEV_DOMID_MASK;  in set_dte_entry()
2074 	 * Restore cached persistent DTE bits, which can be set by information  in set_dte_entry()
2103 	struct dev_table_entry *dte = &get_dev_table(iommu)[dev_data->devid];  in clear_dte_entry()  local
2105 	make_clear_dte(dev_data, dte, &new);  in clear_dte_entry()
2109 /* Update and flush DTE for the given device */
2330 	/* Clear DTE and flush the entry */  in detach_device()
2592 	/* Clear DTE and flush the entry */  in blocked_domain_attach_device()
2800 	struct dev_table_entry *dte;  in amd_iommu_set_dirty_tracking()  local
2816 		dte = &get_dev_table(iommu)[dev_data->devid];  in amd_iommu_set_dirty_tracking()
2817 		new = dte->data[0];  in amd_iommu_set_dirty_tracking()
2819 		dte->data[0] = new;  in amd_iommu_set_dirty_tracking()
2822 		/* Flush device DTE */  in amd_iommu_set_dirty_tracking()
2964 	 *  - SNP is enabled, because it prohibits DTE[Mode]=0.  in amd_iommu_def_domain_type()
3088 	struct dev_table_entry *dte = &get_dev_table(iommu)[devid];  in set_dte_irq_entry()  local
3094 	new = READ_ONCE(dte->data[2]);  in set_dte_irq_entry()
3100 	WRITE_ONCE(dte->data[2], new);  in set_dte_irq_entry()