| /linux-6.14.4/arch/alpha/kernel/ |
| D | sys_marvel.c | 96 ctl = &io7->csrs->PO7_LSI_CTL[irq & 0xff].csr; /* assume LSI */ in io7_get_irq_ctl()
98 ctl = &io7->csrs->PO7_MSI_CTL[((irq - 0x80) >> 5) & 0x0f].csr; in io7_get_irq_ctl()
196 val = io7->csrs->PO7_LSI_CTL[which].csr; in io7_redirect_one_lsi()
200 io7->csrs->PO7_LSI_CTL[which].csr = val; in io7_redirect_one_lsi()
202 io7->csrs->PO7_LSI_CTL[which].csr; in io7_redirect_one_lsi()
213 val = io7->csrs->PO7_MSI_CTL[which].csr; in io7_redirect_one_msi()
217 io7->csrs->PO7_MSI_CTL[which].csr = val; in io7_redirect_one_msi()
219 io7->csrs->PO7_MSI_CTL[which].csr; in io7_redirect_one_msi()
228 io7->csrs->PO7_LSI_CTL[which].csr = ((unsigned long)where << 14); in init_one_io7_lsi()
230 io7->csrs->PO7_LSI_CTL[which].csr; in init_one_io7_lsi()
[all …]
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| D | core_marvel.c | 168 io7_ioport_csrs *csrs; in io7_clear_errors() local
176 csrs = IO7_CSRS_KERN(io7->pe, port); in io7_clear_errors()
178 csrs->POx_ERR_SUM.csr = -1UL; in io7_clear_errors()
179 csrs->POx_TLB_ERR.csr = -1UL; in io7_clear_errors()
180 csrs->POx_SPL_COMPLT.csr = -1UL; in io7_clear_errors()
181 csrs->POx_TRANS_SUM.csr = -1UL; in io7_clear_errors()
205 io7_ioport_csrs *csrs = IO7_CSRS_KERN(io7->pe, port); in io7_init_hose() local
221 io7_port->csrs = csrs; in io7_init_hose()
262 io7_port->saved_wbase[i] = csrs->POx_WBASE[i].csr; in io7_init_hose()
263 io7_port->saved_wmask[i] = csrs->POx_WMASK[i].csr; in io7_init_hose()
[all …]
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| D | err_marvel.c | 818 err_sum |= io7->csrs->PO7_ERROR_SUM.csr; in marvel_find_io7_with_error()
822 err_sum |= io7->ports[i].csrs->POx_ERR_SUM.csr; in marvel_find_io7_with_error()
843 io->io_asic_rev = io7->csrs->IO_ASIC_REV.csr; in marvel_find_io7_with_error()
844 io->io_sys_rev = io7->csrs->IO_SYS_REV.csr; in marvel_find_io7_with_error()
845 io->io7_uph = io7->csrs->IO7_UPH.csr; in marvel_find_io7_with_error()
846 io->hpi_ctl = io7->csrs->HPI_CTL.csr; in marvel_find_io7_with_error()
847 io->crd_ctl = io7->csrs->CRD_CTL.csr; in marvel_find_io7_with_error()
848 io->hei_ctl = io7->csrs->HEI_CTL.csr; in marvel_find_io7_with_error()
849 io->po7_error_sum = io7->csrs->PO7_ERROR_SUM.csr; in marvel_find_io7_with_error()
850 io->po7_uncrr_sym = io7->csrs->PO7_UNCRR_SYM.csr; in marvel_find_io7_with_error()
[all …]
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| /linux-6.14.4/arch/loongarch/include/asm/ |
| D | kvm_csr.h | 47 /* Guest CSRS read and write */
152 /* Guest related CSRs */
182 #define kvm_save_hw_gcsr(csr, gid) (csr->csrs[gid] = gcsr_read(gid))
183 #define kvm_restore_hw_gcsr(csr, gid) (gcsr_write(csr->csrs[gid], gid))
185 #define kvm_read_clear_hw_gcsr(csr, gid) (csr->csrs[gid] = gcsr_write(0, gid))
191 return csr->csrs[gid]; in kvm_read_sw_gcsr()
196 csr->csrs[gid] = val; in kvm_write_sw_gcsr()
202 csr->csrs[gid] |= val; in kvm_set_sw_gcsr()
210 csr->csrs[gid] &= ~_mask; in kvm_change_sw_gcsr()
211 csr->csrs[gid] |= val & _mask; in kvm_change_sw_gcsr()
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| D | kvm_host.h | 139 unsigned long csrs[CSR_MAX_NUMS]; member
184 /* Host CSRs are used when handling exits from guest */
254 return csr->csrs[reg]; in readl_sw_gcsr()
259 csr->csrs[reg] = val; in writel_sw_gcsr()
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| /linux-6.14.4/arch/alpha/include/asm/ |
| D | core_t2.h | 60 /* The CSRs below are T3/T4 only */
87 /* T2 CSRs are in the non-cachable primary IO space from 3.8000.0000 to
91 * | CPU 0 CSRs |
93 * | CPU 1 CSRs |
95 * | CPU 2 CSRs |
97 * | CPU 3 CSRs |
103 * | Mem 0 CSRs |
105 * | Mem 1 CSRs |
107 * | Mem 2 CSRs |
109 * | Mem 3 CSRs |
[all …]
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| /linux-6.14.4/Documentation/devicetree/bindings/net/pcs/ |
| D | snps,dw-xpcs.yaml | 21 The PCS CSRs can be accessible either over the Ethernet MDIO bus or directly
49 of the MDIO bus device. If DW XPCS CSRs space is accessed over the
57 so the corresponding subset would be mapped to the lowest 255 CSRs.
65 The way the CSRs are mapped to the memory is platform depended. Since
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| /linux-6.14.4/Documentation/devicetree/bindings/pci/ |
| D | snps,dw-pcie-ep.yaml | 47 with all spaces. Note iATU/eDMA CSRs are indirectly accessible
73 set of viewport CSRs mapped into the PL space. Note iATU is
79 CSRs mapped in a non-standard base address. The registers offset
86 PCS and PHY CSRs accessible over a dedicated memory mapped
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| D | snps,dw-pcie.yaml | 56 with all spaces. Note iATU/eDMA CSRs are indirectly accessible
82 set of viewport CSRs mapped into the PL space. Note iATU is
88 CSRs mapped in a non-standard base address. The registers offset
95 PCS and PHY CSRs accessible over a dedicated memory mapped
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| /linux-6.14.4/include/linux/ |
| D | litex.h | 4 * helper functions for accessing CSRs.
34 * means that only larger-than-32-bit CSRs will be split across multiple
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| /linux-6.14.4/Documentation/devicetree/bindings/interrupt-controller/ |
| D | riscv,cpu-intc.yaml | 10 RISC-V cores include Control Status Registers (CSRs) which are local to
12 software. Some of these CSRs are used to control local interrupts connected
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| /linux-6.14.4/arch/riscv/kernel/ |
| D | fpu.S | 26 csrs CSR_STATUS, t1
70 csrs CSR_STATUS, t1
127 csrs CSR_STATUS, t1
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| D | suspend_entry.S | 45 /* Save CSRs */
84 /* Restore CSRs */
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| D | suspend.c | 62 /* Save additional CSRs*/ in cpu_suspend()
90 /* Restore additional CSRs */ in cpu_suspend()
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| D | head.S | 401 csrs CSR_STATUS, t1
451 csrs CSR_STATUS, t1
452 csrs CSR_VCSR, x0
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| /linux-6.14.4/drivers/net/ethernet/netronome/nfp/nfpcore/ |
| D | nfp_arm.h | 145 /* Gasket CSRs */
151 /* BAR CSRs
210 /* MP Core CSRs */
213 /* PL320 CSRs */
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| /linux-6.14.4/tools/arch/riscv/include/asm/ |
| D | csr.h | 309 /* Supervisor-Level High-Half CSRs (AIA) */
356 /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
365 /* Hypervisor stateen CSRs */
400 /* Machine-Level High-Half CSRs (AIA) */
517 __asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" \
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| /linux-6.14.4/arch/riscv/include/asm/ |
| D | csr.h | 341 /* Supervisor-Level High-Half CSRs (AIA) */
388 /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
397 /* Hypervisor stateen CSRs */
434 /* Machine-Level High-Half CSRs (AIA) */
556 __asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" \
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| /linux-6.14.4/arch/riscv/kvm/ |
| D | vcpu_switch.S | 277 csrs CSR_SSTATUS, t1
319 csrs CSR_SSTATUS, t1
362 csrs CSR_SSTATUS, t1
404 csrs CSR_SSTATUS, t1
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| D | vcpu.c | 99 /* Reset the guest CSRs for hotplug usecase */ in kvm_riscv_reset_vcpu()
134 /* Setup reset state of shadow SSTATUS and HSTATUS CSRs */ in kvm_arch_vcpu_create()
375 /* Read current HVIP and VSIE CSRs */ in kvm_riscv_vcpu_sync_interrupts()
402 /* Sync-up timer CSRs */ in kvm_riscv_vcpu_sync_interrupts()
784 * We save trap CSRs (such as SEPC, SCAUSE, STVAL, HTVAL, and in kvm_riscv_vcpu_enter_exit()
788 * potentially change trap CSRs. in kvm_riscv_vcpu_enter_exit()
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| /linux-6.14.4/drivers/infiniband/hw/hfi1/ |
| D | chip.h | 580 * per-context or per-SDMA CSRs that are not mappable to user-space.
586 /* kernel per-context CSRs are separated by 0x100 */ in read_kctxt_csr()
593 /* kernel per-context CSRs are separated by 0x100 */ in write_kctxt_csr()
614 * per-context CSRs that are mappable to user space. All these CSRs
616 * different processes without exposing other contexts' CSRs
621 /* user per-context CSRs are separated by 0x1000 */ in read_uctxt_csr()
628 /* user per-context CSRs are separated by 0x1000 */ in write_uctxt_csr()
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| /linux-6.14.4/drivers/net/ethernet/marvell/octeontx2/af/ |
| D | lmac_common.h | 57 /* Features like RXSTAT, TXSTAT, DMAC FILTER csrs differs by fixed
158 /* Lock to serialize read/write of global csrs like
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| /linux-6.14.4/drivers/pci/controller/dwc/ |
| D | pcie-designware.h | 149 * iATU inbound and outbound windows CSRs. Before the IP-core v4.80a each
150 * iATU region CSRs had been indirectly accessible by means of the dedicated
151 * viewport selector. The iATU/eDMA CSRs space was re-designed in DWC PCIe
153 * iATU/eDMA CSRs space.
193 * eDMA CSRs. DW PCIe IP-core v4.70a and older had the eDMA registers accessible
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| /linux-6.14.4/drivers/tty/serial/ |
| D | liteuart.c | 23 * CSRs definitions (base address offsets + width)
29 * generic way of indexing the LiteX CSRs.
31 * For more details on how CSRs are defined and handled in LiteX, see comments
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| /linux-6.14.4/drivers/net/ethernet/sfc/falcon/ |
| D | io.h | 22 * Many CSRs are very wide and cannot be read or written atomically.
30 * Writes to different CSRs and 64-bit SRAM words must be serialised,
34 * We also serialise reads from 128-bit CSRs and SRAM with the same
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