Home
last modified time | relevance | path

Searched full:clk_top_venc_sel (Results 1 – 17 of 17) sorted by relevance

/linux-6.14.4/Documentation/devicetree/bindings/media/
Dmediatek,vcodec-encoder.yaml161 clocks = <&topckgen CLK_TOP_VENC_SEL>;
163 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
/linux-6.14.4/Documentation/devicetree/bindings/soc/mediatek/
Dscpsys.txt69 <&topckgen CLK_TOP_VENC_SEL>,
/linux-6.14.4/include/dt-bindings/clock/
Dmt8135-clk.h86 #define CLK_TOP_VENC_SEL 75 macro
Dmediatek,mt6795-clk.h96 #define CLK_TOP_VENC_SEL 85 macro
Dmt8173-clk.h98 #define CLK_TOP_VENC_SEL 88 macro
Dmt2712-clk.h135 #define CLK_TOP_VENC_SEL 104 macro
Dmt8192-clk.h63 #define CLK_TOP_VENC_SEL 51 macro
/linux-6.14.4/Documentation/devicetree/bindings/power/
Dmediatek,power-controller.yaml170 <&topckgen CLK_TOP_VENC_SEL>;
/linux-6.14.4/arch/arm64/boot/dts/mediatek/
Dmt8173.dtsi466 <&topckgen CLK_TOP_VENC_SEL>;
1474 clocks = <&topckgen CLK_TOP_VENC_SEL>;
1476 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
Dmt6795.dtsi311 <&topckgen CLK_TOP_VENC_SEL>;
Dmt8192.dtsi628 clocks = <&topckgen CLK_TOP_VENC_SEL>,
1827 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
Dmt2712e.dtsi287 <&topckgen CLK_TOP_VENC_SEL>,
/linux-6.14.4/drivers/clk/mediatek/
Dclk-mt6795-topckgen.c462 TOP_MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x50, 16, 4, 23, 0),
Dclk-mt8135.c373 MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x0150, 8, 3, 15),
Dclk-mt8173-topckgen.c541 MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x0050, 16, 4, 23),
Dclk-mt2712.c652 MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x050, 16, 4, 23),
Dclk-mt8192.c667 MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC_SEL, "venc_sel",