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/linux-6.14.4/Documentation/devicetree/bindings/soc/qcom/
Dqcom,geni-se.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <[email protected]>
23 - qcom,geni-se-qup
24 - qcom,geni-se-i2c-master-hub
30 clock-names:
38 "#address-cells":
41 "#size-cells":
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/mfd/
Datmel,at91sam9260-matrix.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/atmel,at91sam9260-matrix.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Ferre <[email protected]>
13 The Bus Matrix (MATRIX) implements a multi-layer AHB, based on the
14 AHB-Lite protocol, that enables parallel access paths between multiple
20 - items:
21 - enum:
22 - atmel,at91sam9260-matrix
[all …]
/linux-6.14.4/drivers/ata/
Dsata_dwc_460ex.c1 // SPDX-License-Identifier: GPL-2.0-or-later
38 #define DRV_NAME "sata-dwc"
123 struct ata_probe_ent *pe; /* ptr to probe-ent */
155 #define HSDEV_FROM_HOST(host) ((struct sata_dwc_device *)(host)->private_data)
156 #define HSDEV_FROM_AP(ap) ((struct sata_dwc_device *)(ap)->host->private_data)
157 #define HSDEVP_FROM_AP(ap) ((struct sata_dwc_device_port *)(ap)->private_data)
158 #define HSDEV_FROM_QC(qc) ((struct sata_dwc_device *)(qc)->ap->host->private_data)
159 #define HSDEV_FROM_HSDEVP(p) ((struct sata_dwc_device *)(p)->hsdev)
182 #include <linux/platform_data/dma-dw.h>
196 if (dws->dma_dev != chan->device->dev) in sata_dwc_dma_filter()
[all …]
Dsata_fsl.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 * Copyright (c) 2006-2007, 2011-2012 Freescale Semiconductor, Inc.
34 "INT coalescing timer threshold in AHB ticks");
39 SATA_FSL_MAX_PRD_USABLE = SATA_FSL_MAX_PRD - 1,
51 * SATA-FSL host controller supports a max. of (15+1) direct PRDEs, and
96 ICC_MAX_INT_COUNT_THRESHOLD = ((1 << 5) - 1),
98 ICC_MAX_INT_TICKS_THRESHOLD = ((1 << 19) - 1),
103 * Host Controller command register set - per port
209 /* TRANSCFG (transport-layer) configuration control */
214 /* PHY (link-layer) configuration control */
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/linux-6.14.4/drivers/soc/qcom/
Dqcom-geni-se.c1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
10 #include <linux/dma-mapping.h>
17 #include <linux/soc/qcom/geni-se.h>
31 * GENI based QUP is a highly-flexible and programmable module for supporting
35 * platform configuration. The protocol supported by each interface is
41 * +-----------------------------------------+
43 * | +----------------------------+ |
44 * --QUP & SE Clocks--> | Serial Engine N | +-IO------>
46 * <---Clock Perf.----+ +----+-----------------------+ | |
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/linux-6.14.4/Documentation/devicetree/bindings/dma/
Datmel,sama5d4-dma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/atmel,sama5d4-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Ferre <[email protected]>
11 - Charan Pedumuru <[email protected]>
14 The DMA Controller (XDMAC) is a AHB-protocol central direct memory access
18 or memory-to-memory transfers. The channel features are configurable at
22 - $ref: dma-controller.yaml#
27 - enum:
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/linux-6.14.4/Documentation/devicetree/bindings/spi/
Dqcom,spi-qcom-qspi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/qcom,spi-qcom-qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <[email protected]>
12 description: The QSPI controller allows SPI protocol communication in single,
17 - $ref: /schemas/spi/spi-controller.yaml#
22 - enum:
23 - qcom,sc7180-qspi
24 - qcom,sc7280-qspi
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Dqcom,spi-qup.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/qcom,spi-qup.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andy Gross <[email protected]>
11 - Bjorn Andersson <[email protected]>
12 - Krzysztof Kozlowski <[email protected]>
15 The QUP core is an AHB slave that provides a common data path (an output FIFO
16 and an input FIFO) for serial peripheral interface (SPI) mini-core.
19 programmable data path from 4 bits to 32 bits and numerous protocol variants.
[all …]
Dqcom,spi-geni-qcom.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/qcom,spi-geni-qcom.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andy Gross <[email protected]>
11 - Bjorn Andersson <[email protected]>
12 - Krzysztof Kozlowski <[email protected]>
15 The QUP v3 core is a GENI based AHB slave that provides a common data path
17 mini-core.
20 programmable data path from 4 bits to 32 bits and numerous protocol variants.
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/net/dsa/
Drenesas,rzn1-a5psw.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/dsa/renesas,rzn1-a5psw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Clément Léger <[email protected]>
17 - $ref: dsa.yaml#/$defs/ethernet-ports
22 - enum:
23 - renesas,r9a06g032-a5psw
24 - const: renesas,rzn1-a5psw
31 - description: Device Level Ring (DLR) interrupt
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/linux-6.14.4/drivers/usb/host/
Docteon-hcd.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 * Copyright (c) 2003-2010 Cavium Networks ([email protected]). All rights
102 * Core AHB Configuration Register (GAHBCFG)
104 * This register can be used to configure the core after power-on or a change in
105 * mode of operation. This register mainly contains AHB system-related
106 * configuration parameters. The AHB is the processor interface to the O2P USB
126 * @nptxfemplvl: Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl)
128 * Indicates when the Non-Periodic TxFIFO Empty Interrupt bit in
131 * * 1'b0: GINTSTS.NPTxFEmp interrupt indicates that the Non-
133 * * 1'b1: GINTSTS.NPTxFEmp interrupt indicates that the Non-
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/linux-6.14.4/arch/arm64/boot/dts/freescale/
Dimx8ulp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8ulp-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/power/imx8ulp-power.h>
10 #include <dt-bindings/thermal/thermal.h>
12 #include "imx8ulp-pinfunc.h"
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
[all …]
Ds32g3.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright 2021-2024 NXP
7 * Andra-Teodora Ilie <[email protected]>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <0x02>;
16 #size-cells = <0x02>;
19 #address-cells = <1>;
20 #size-cells = <0>;
22 cpu-map {
[all …]
Ds32g2.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 * Copyright 2017-2021, 2024 NXP
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
17 reserved-memory {
18 #address-cells = <2>;
19 #size-cells = <2>;
23 compatible = "arm,scmi-shmem";
[all …]
Dimx95.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
6 #include <dt-bindings/dma/fsl-edma.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
12 #include "imx95-clock.h"
13 #include "imx95-pinfunc.h"
14 #include "imx95-power.h"
17 interrupt-parent = <&gic>;
[all …]
/linux-6.14.4/drivers/crypto/gemini/
Dsl3516-ce-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * sl3516-ce-core.c - hardware cryptographic offloader for Storlink SL3516 SoC
16 #include <linux/dma-mapping.h>
28 #include "sl3516-ce.h"
35 ce->tx = dma_alloc_coherent(ce->dev, sz, &ce->dtx, GFP_KERNEL); in sl3516_ce_desc_init()
36 if (!ce->tx) in sl3516_ce_desc_init()
37 return -ENOMEM; in sl3516_ce_desc_init()
38 ce->rx = dma_alloc_coherent(ce->dev, sz, &ce->drx, GFP_KERNEL); in sl3516_ce_desc_init()
39 if (!ce->rx) in sl3516_ce_desc_init()
43 ce->tx[i].frame_ctrl.bits.own = CE_CPU; in sl3516_ce_desc_init()
[all …]
Dsl3516-ce.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sl3516-ce.h - hardware cryptographic offloader for cortina/gemini SoC
11 * The CE was designed to handle IPSEC and wifi(TKIP WEP) protocol.
90 * struct sl3516_ce_descriptor - descriptor for CE operations
100 * struct desc_frame_ctrl - Information for the current descriptor
107 * @perr: Protocol error during processing this descriptor
125 * struct desc_flag_status - flag for this descriptor
140 * struct desc_next - describe chaining of descriptors
144 * @dec: AHB bus address increase (0), decrease (1)
158 * struct control - The value of this register is used to set the
[all …]
/linux-6.14.4/drivers/dma/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
97 tristate "Atmel AHB DMA support"
102 Support the Atmel AHB DMA controller.
112 tristate "Analog Devices AXI-DMAC DMA support"
118 Enable support for the Analog Devices AXI-DMAC peripheral. This DMA
154 tristate "SA-11x0 DMA support"
159 Support the DMA engine found on Intel StrongARM SA-1100 and
160 SA-1110 SoCs. This DMA engine can only be used with on-chip
220 This module can be found on Freescale Vybrid and LS-1 SoCs.
263 Enable support for the IMG multi-threaded DMA controller (MDC).
[all …]
/linux-6.14.4/drivers/net/ethernet/cortina/
Dgemini.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2008-2009 Paulius Zaleckas <[email protected]>
6 * Copyright (C) 2010 Michał Mirosław <mirq-[email protected]>
49 * GMAC 0/1 SW TX Q0-5, and GMAC 0/1 HW TX Q0-5
58 #define __RWPTR_PREV(x, mask) (((unsigned int)(x) - 1) & (mask))
59 #define __RWPTR_DISTANCE(r, w, mask) (((unsigned int)(w) - (r)) & (mask))
60 #define __RWPTR_MASK(order) ((1 << (order)) - 1)
136 /* Support Protocol Register 0 */
145 /* GMAC Hash/Rx/Tx AHB Weighting register */
274 #define TOE_QH_FULL_INT_BIT(x) BIT(x - 32)
[all …]
/linux-6.14.4/drivers/usb/dwc2/
Dhcd_intr.c1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * hcd_intr.c - DesignWare HS OTG Controller host-mode interrupt handling
5 * Copyright (C) 2004-2013 Synopsys, Inc.
15 #include <linux/dma-mapping.h>
35 u16 curr_frame_number = hsotg->frame_number; in dwc2_track_missed_sofs()
36 u16 expected = dwc2_frame_num_inc(hsotg->last_frame_num, 1); in dwc2_track_missed_sofs()
43 if (hsotg->frame_num_idx < FRAME_NUM_ARRAY_SIZE) { in dwc2_track_missed_sofs()
45 hsotg->frame_num_array[hsotg->frame_num_idx] = in dwc2_track_missed_sofs()
47 hsotg->last_frame_num_array[hsotg->frame_num_idx] = in dwc2_track_missed_sofs()
48 hsotg->last_frame_num; in dwc2_track_missed_sofs()
[all …]
/linux-6.14.4/drivers/spi/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
10 protocol. Chips that support SPI can have data transfer rates
13 dynamic device discovery; some are even write-only or read-only.
17 chips, analog to digital (and d-to-a) converters, and more.
18 MMC and SD cards can be accessed using SPI protocol; and for
33 sysfs, and debugfs support in SPI controller and protocol drivers.
44 If your system has an master-capable SPI controller (which
46 controller and the protocol drivers for the SPI slave chips
56 by providing a high-level interface to send memory-like commands.
66 This enables support for SPI-NAND mode on the Airoha NAND
[all …]
/linux-6.14.4/drivers/usb/gadget/udc/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
7 # NOTE: Gadget support ** DOES NOT ** depend on host-side CONFIG_USB !!
9 # - Host systems (like PCs) need CONFIG_USB (with "A" jacks).
10 # - Peripherals (like PDAs) need CONFIG_USB_GADGET (with "B" jacks).
11 # - Some systems have both kinds of controllers.
13 # With help from a special transceiver and a "Mini-AB" jack, systems with
14 # both kinds of controller can also support "USB On-the-Go" (CONFIG_USB_OTG).
22 # - integrated/SOC controllers first
23 # - licensed IP used in both SOC and discrete versions
24 # - discrete ones (including all PCI-only controllers)
[all …]
/linux-6.14.4/drivers/net/wireless/ath/carl9170/
Dhw.h4 * Register map, hardware-specific definitions
7 * Copyright 2009-2011 Christian Lamparter <[email protected]>
24 * Copyright (c) 2007-2008 Atheros Communications, Inc.
387 #define AR9170_MAC_BCN_LENGTH_MAX (512 - 32)
449 /* WPS Button GPIO for TP-Link TL-WN821N */
727 /* PCI/USB to AHB Bridge */
749 * PCI to AHB Bridge
783 /* Protocol Controller Module */
/linux-6.14.4/drivers/net/ethernet/faraday/
Dftgmac100.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * (C) Copyright 2009-2011 Faraday Technology
6 * Po-Yu Chuang <ratbert@faraday-tech.com>
12 #include <linux/dma-mapping.h>
54 /* For NC-SI to register a fixed-link phy device */
126 struct net_device *netdev = priv->netdev; in ftgmac100_reset_mac()
130 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR); in ftgmac100_reset_mac()
132 priv->base + FTGMAC100_OFFSET_MACCR); in ftgmac100_reset_mac()
136 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR); in ftgmac100_reset_mac()
144 return -EIO; in ftgmac100_reset_mac()
[all …]
/linux-6.14.4/drivers/net/ethernet/actions/
Dowl-emac.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <linux/dma-mapping.h>
19 #include "owl-emac.h"
27 return readl(priv->base + reg); in owl_emac_reg_read()
32 writel(data, priv->base + reg); in owl_emac_reg_write()
63 return priv->netdev->dev.parent; in owl_emac_get_dev()
129 return dma_map_single(dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE); in owl_emac_dma_map_tx()
142 return CIRC_SPACE(ring->head, ring->tail, ring->size); in owl_emac_ring_num_unused()
148 return (cur + 1) & (ring->size - 1); in owl_emac_ring_get_next()
153 ring->head = owl_emac_ring_get_next(ring, ring->head); in owl_emac_ring_push_head()
[all …]

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