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/linux-6.14.4/Documentation/devicetree/bindings/timer/
Drenesas,cmt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <[email protected]>
11 - Laurent Pinchart <[email protected]>
14 The CMT is a multi-channel 16/32/48-bit timer/counter with configurable clock
26 - items:
27 - enum:
28 - renesas,r8a7740-cmt0 # 32-bit CMT0 on R-Mobile A1
29 - renesas,r8a7740-cmt1 # 48-bit CMT1 on R-Mobile A1
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/linux-6.14.4/Documentation/arch/arm64/
Dmemory.rst12 with the 4KB page configuration, allowing 39-bit (512GB) or 48-bit
14 64KB pages, only 2 levels of translation tables, allowing 42-bit (4TB)
21 TTBRx selection is given by bit 55 of the virtual address. The
23 contains only user (non-global) mappings. The swapper_pg_dir address is
36 52-bit VA support in the kernel
37 -------------------------------
38 If the ARMv8.2-LVA optional feature is present, and we are running
39 with a 64KB page size; then it is possible to use 52-bits of address
41 binary that supports 52-bit must also be able to fall back to 48-bit
45 higher addresses such that they are invariant to 48/52-bit VAs. Due
[all …]
/linux-6.14.4/drivers/gpio/
Dgpio-104-idi-48.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * GPIO driver for the ACCES 104-IDI-48 family
6 * This driver supports the following ACCES devices: 104-IDI-48A,
7 * 104-IDI-48AC, 104-IDI-48B, and 104-IDI-48BC.
29 MODULE_PARM_DESC(base, "ACCES 104-IDI-48 base addresses");
34 MODULE_PARM_DESC(irq, "ACCES 104-IDI-48 interrupt line numbers");
49 *mask = BIT(line); in idi_48_reg_mask_xlate()
87 #define IDI48_NGPIO 48
91 .mask = BIT((_id) / 8), \
96 IDI48_REGMAP_IRQ(0), IDI48_REGMAP_IRQ(1), IDI48_REGMAP_IRQ(2), /* 0-2 */
[all …]
/linux-6.14.4/include/uapi/linux/
Ddccp.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
9 * struct dccp_hdr - generic part of DCCP packet header
11 * @dccph_sport - Relevant port on the endpoint that sent this packet
12 * @dccph_dport - Relevant port on the other endpoint
13 * @dccph_doff - Data Offset from the start of the DCCP header, in 32-bit words
14 * @dccph_ccval - Used by the HC-Sender CCID
15 * @dccph_cscov - Parts of the packet that are covered by the Checksum field
16 * @dccph_checksum - Internet checksum, depends on dccph_cscov
17 * @dccph_x - 0 = 24 bit sequence number, 1 = 48
18 * @dccph_type - packet type, see DCCP_PKT_ prefixed macros
[all …]
Dhdreg.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
17 #define IDE_DRIVE_TASK_INVALID -1
137 * 0x01->0x02 Reserved
141 * 0x04->0x07 Reserved
146 * 0x09->0x0F Reserved
151 * 0x10->0x1F Reserved
153 #define WIN_READ 0x20 /* 28-Bit */
154 #define WIN_READ_ONCE 0x21 /* 28-Bit without retries */
155 #define WIN_READ_LONG 0x22 /* 28-Bit */
156 #define WIN_READ_LONG_ONCE 0x23 /* 28-Bit without retries */
[all …]
/linux-6.14.4/arch/mips/include/asm/sgi/
Dheart.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2004-2007 Stanislaw Skowronek <[email protected]>
7 * 2007-2015 Joshua Kinard <[email protected]>
27 * struct ip30_heart_regs - struct that maps IP30 HEART registers.
28 * @mode: HEART_MODE - Purpose Unknown, machine reset called from here.
29 * @sdram_mode: HEART_SDRAM_MODE - purpose unknown.
30 * @mem_refresh: HEART_MEM_REF - purpose unknown.
31 * @mem_req_arb: HEART_MEM_REQ_ARB - purpose unknown.
32 * @mem_cfg.q: union for 64bit access to HEART_MEMCFG - 4x 64bit registers.
33 * @mem_cfg.l: union for 32bit access to HEART_MEMCFG - 8x 32bit registers.
[all …]
/linux-6.14.4/arch/arm/lib/
Dcrc-t10dif-core.S2 // Accelerated CRC-T10DIF using ARM NEON and Crypto Extensions instructions
14 // Implement fast CRC-T10DIF computation with SSE and PCLMULQDQ instructions
62 // /white-papers/fast-crc-computation-generic-polynomials-pclmulqdq-paper.pdf
75 .arch armv8-a
76 .fpu crypto-neon-fp-armv8
116 * Pairwise long polynomial multiplication of two 16-bit values
120 * by two 64-bit values
125 * significant. The resulting 80-bit vectors are XOR'ed together.
139 * 6 (w0*x6 ^ w1*x5) << 48 ^ | (y0*z6 ^ y1*z5) << 48 ^
148 * and after performing 8x8->16 bit long polynomial multiplication of
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/linux-6.14.4/Documentation/sound/cards/
Daudiophile-usb.rst2 Guide to using M-Audio Audiophile USB with ALSA and Jack
9 This document is a guide to using the M-Audio Audiophile USB (tm) device with
15 * v1.4 - Thibault Le Meur (2007-07-11)
17 - Added Low Endianness nature of 16bits-modes
19 - Modifying document structure
21 * v1.5 - Thibault Le Meur (2007-07-12)
22 - Added AC3/DTS passthru info
35 - This port supports 2 pairs of line-level audio inputs (1/4" TS and RCA)
36 - When the 1/4" TS (jack) connectors are connected, the RCA connectors
52 Please exit any audio application running before switching between bit depths
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/linux-6.14.4/arch/arm64/lib/
Dcrc-t10dif-core.S2 // Accelerated CRC-T10DIF using arm64 NEON and Crypto Extensions instructions
5 // Copyright (C) 2019-2024 Google LLC
17 // Implement fast CRC-T10DIF computation with SSE and PCLMULQDQ instructions
65 // /white-papers/fast-crc-computation-generic-polynomials-pclmulqdq-paper.pdf
72 .arch armv8-a+crypto
96 * Pairwise long polynomial multiplication of two 16-bit values
100 * by two 64-bit values
119 * 6 (w0*x6 ^ w1*x5) << 48 ^ | (y0*z6 ^ y1*z5) << 48 ^
128 * and after performing 8x8->16 bit long polynomial multiplication of
130 * we obtain the following four vectors of 16-bit elements:
[all …]
/linux-6.14.4/arch/powerpc/kernel/vdso/
Dsigtramp32.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
23 .Lsig_start = . - 4
43 .uleb128 9f - 1f; /* length */ \
56 .uleb128 9f - 1f; /* length */ \
65 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
72 .uleb128 9f - 1f; /* length */ \
97 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
102 .uleb128 9f - 1f; /* length */ \
105 .byte 0x2f; .short 2b - 9f; /* DW_OP_skip */ \
108 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset OFS of
[all …]
Dsigtramp64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
42 .quad 0,-21*8
48 .uleb128 9f - 1f; /* length */ \
61 .uleb128 9f - 1f; /* length */ \
70 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
77 .uleb128 9f - 1f; /* length */ \
103 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
108 .uleb128 9f - 1f; /* length */ \
111 .byte 0x2f; .short 2b - 9f; /* DW_OP_skip */ \
114 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset OFS of
[all …]
/linux-6.14.4/arch/x86/lib/
Dcrct10dif-pcl-asm_64.S2 # Implement fast CRC-T10DIF computation with SSE and PCLMULQDQ instructions
50 # /white-papers/fast-crc-computation-generic-polynomials-pclmulqdq-paper.pdf
106 # bit order match the polynomial coefficient order.
136 # While >= 128 data bytes remain (not counting xmm0-7), fold the 128
137 # bytes xmm0-7 into them, storing the result back into xmm0-7.
147 # Now fold the 112 bytes in xmm0-xmm6 into the 16 bytes in xmm7.
167 add $128-16, len
200 movdqu -16(buf, len), %xmm1
203 # xmm2 = high order part of second chunk: xmm7 left-shifted by 'len' bytes.
209 # xmm7 = first chunk: xmm7 right-shifted by '16-len' bytes.
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/linux-6.14.4/drivers/net/ethernet/microsoft/mana/
Dshm_channel.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
17 #define SHMEM_VF_RESET_STATE ((u32)-1)
38 * direction: 0 for request, VF->PF; 1 for response, PF->VF.
67 #define SMC_LAST_DWORD (SMC_APERTURE_DWORDS - 1)
75 /* Poll the hardware for the ownership bit. This should be pretty fast, in mana_smc_poll_register()
87 if (!(last_dword & BIT(31))) in mana_smc_poll_register()
93 return -ETIMEDOUT; in mana_smc_poll_register()
99 void __iomem *base = sc->base; in mana_smc_read_response()
116 dev_err(sc->dev, "Wrong SMC response 0x%x, type=%d, ver=%d\n", in mana_smc_read_response()
118 return -EPROTO; in mana_smc_read_response()
[all …]
/linux-6.14.4/Documentation/core-api/
Dpacking.rst6 -----------------
10 One can memory-map a pointer to a carefully crafted struct over the hardware
15 definitions from the hardware documentation into bit field indices for the
18 (sometimes even 64 bit ones). This creates the inconvenience of having to
23 were performed byte-by-byte. Also the code can easily get cluttered, and the
24 high-level idea might get lost among the many bit shifts required.
25 Many drivers take the bit-shifting approach and then attempt to reduce the
30 ------------
34 - Packing a CPU-usable number into a memory buffer (with hardware
36 - Unpacking a memory buffer (which has hardware constraints/quirks)
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/linux-6.14.4/sound/pci/emu10k1/
Dp16v.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (c) by James Courtier-Dutton <[email protected]>
11 /* Audigy2 P16V pointer-offset register set, accessed through the PTR2 and DATA2 registers …
25 #define PLAYBACK_LIST_SIZE 0x01 /* Size of list in bytes << 16. E.g. 8 periods -> 0x00380000 */
73 * [19:16] Playback mixer output enable. 1 bit per channel.
74 * [23:20] Capture mixer output enable. 1 bit per channel.
75 * [26:24] FX engine channel capture 0 = 0x60-0x67.
76 * 1 = 0x68-0x6f.
77 * 2 = 0x70-0x77.
78 * 3 = 0x78-0x7f.
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/linux-6.14.4/include/sound/
Demu10k1.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
16 #include <sound/pcm-indirect.h>
25 /* ------------------- DEFINES -------------------- */
28 #define MAXPAGES0 4096 /* 32 bit mode */
29 #define MAXPAGES1 8192 /* 31 bit mode */
33 /* FIXME? - according to the OSS driver the EMU10K1 needs a 29 bit DMA mask */
34 #define EMU10K1_DMA_MASK 0x7fffffffUL /* 31bit */
35 #define AUDIGY_DMA_MASK 0xffffffffUL /* 32bit mode */
41 // This is used to define hardware bit-fields (sub-registers) by combining
42 // the bit shift and count with the actual register address. The passed
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/linux-6.14.4/arch/mips/loongson64/
Ddma.c1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/dma-direct.h>
10 /* We extract 2bit node id (bit 44~47, only bit 44~45 used now) from in phys_to_dma()
11 * Loongson-3's 48bit address space and embed it into 40bit */ in phys_to_dma()
19 /* We extract 2bit node id (bit 44~47, only bit 44~45 used now) from in dma_to_phys()
20 * Loongson-3's 48bit address space and embed it into 40bit */ in dma_to_phys()
/linux-6.14.4/arch/alpha/kernel/
Dsys_wildfire.c1 // SPDX-License-Identifier: GPL-2.0
41 int qbbno = (irq >> 8) & (WILDFIRE_MAX_QBB - 1); in wildfire_update_irq_hw()
42 int pcano = (irq >> 6) & (WILDFIRE_PCA_PER_QBB - 1); in wildfire_update_irq_hw()
49 " got irq %d for non-existent PCA %d" in wildfire_update_irq_hw()
57 enable0 = (unsigned long *) &pca->pca_int[0].enable; /* ??? */ in wildfire_update_irq_hw()
72 enable0 = (unsigned long *) &pca->pca_int[0].enable; in wildfire_init_irq_hw()
73 enable1 = (unsigned long *) &pca->pca_int[1].enable; in wildfire_init_irq_hw()
74 enable2 = (unsigned long *) &pca->pca_int[2].enable; in wildfire_init_irq_hw()
75 enable3 = (unsigned long *) &pca->pca_int[3].enable; in wildfire_init_irq_hw()
77 target0 = (unsigned long *) &pca->pca_int[0].target; in wildfire_init_irq_hw()
[all …]
/linux-6.14.4/drivers/gpu/drm/amd/amdkfd/
Dkfd_flat_memory.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright 2014-2022 Advanced Micro Devices, Inc.
45 * Access to ATC/IOMMU mapped memory w/ associated extension of VA to 48b
58 * System Unified Address - SUA
82 * HSA64 - ATC/IOMMU 64b
87 * so the actual VA carried to translation is 48b. There is a “hole” in
107 * to a 49b address. This 49b address is constituted of an “ATC” bit
108 * plus a 48b virtual address. This 49b address is what is passed to the
109 * translation hardware. ATC==0 means the 48b address is a GPUVM address
111 * ATC==1 means the 48b address is intended to be translated via IOMMU
[all …]
/linux-6.14.4/drivers/gpu/drm/xe/
Dxe_lmtt_ml.c1 // SPDX-License-Identifier: MIT
15 * DOC: Multi-Level LMTT Structure
17 * LMHAW (Local Memory Host Address Width) is 48 bit (256TB)
19 * LMGAW (Local Memory Guest Address Width) is 48 bit (256TB)
25 * +-----------+ +-----------+
27 * | | +-----------+ | |
29 * | | | | GDPA --> | PTE | => LMEM PF offset
33 * | | offset -> | PTE | ----------> +-----------+
34 * | | GAW-1:35 +===========+ / \.
36 * VFID --> | PDE | ---------> +-----------+ / \.
[all …]
/linux-6.14.4/include/soc/fsl/
Dbman.h1 /* Copyright 2008 - 2016 Freescale Semiconductor, Inc.
34 /* wrapper for 48-bit buffers */
38 __be16 bpid; /* hi 8-bits reserved */
39 __be16 hi; /* High 16-bits of 48-bit address */
40 __be32 lo; /* Low 32-bits of 48-bit address */
46 * Restore the 48 bit address previously stored in BMan
51 return be64_to_cpu(buf->data) & 0xffffffffffffLLU; in bm_buf_addr()
56 return be64_to_cpu(buf->data) & 0xffffffffffffLLU; in bm_buffer_get64()
61 buf->hi = cpu_to_be16(upper_32_bits(addr)); in bm_buffer_set64()
62 buf->lo = cpu_to_be32(lower_32_bits(addr)); in bm_buffer_set64()
[all …]
/linux-6.14.4/drivers/net/ethernet/apm/xgene/
Dxgene_enet_hw.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* Applied Micro X-Gene SoC Ethernet Driver
22 u32 end = start + len - 1; in xgene_set_bits()
41 #define OVERWRITE BIT(31)
42 #define IS_BUFFER_POOL BIT(20)
43 #define PREFETCH_BUF_EN BIT(21)
61 #define CREATE_MASK(pos, len) GENMASK((pos)+(len)-1, (pos))
62 #define CREATE_MASK_ULL(pos, len) GENMASK_ULL((pos)+(len)-1, (pos))
92 #define ACCEPTLERR BIT(19)
93 #define QCOHERENT BIT(4)
[all …]
/linux-6.14.4/drivers/crypto/marvell/octeontx/
Dotx_cpt_hw_types.h1 /* SPDX-License-Identifier: GPL-2.0
46 #define OTX_CPT_VF_INTR_MBOX_MASK BIT(0)
47 #define OTX_CPT_VF_INTR_DOVF_MASK BIT(1)
48 #define OTX_CPT_VF_INTR_IRDE_MASK BIT(2)
49 #define OTX_CPT_VF_INTR_NWRP_MASK BIT(3)
50 #define OTX_CPT_VF_INTR_SERR_MASK BIT(4)
154 * CPT OcteonTX VF MSI-X Vector Enumeration
155 * Enumerates the MSI-X interrupt vectors.
167 * stored in memory as little-endian unless CPT()_PF_Q()_CTL[INST_BE] is set.
179 * Address must be 16-byte aligned.
[all …]
/linux-6.14.4/drivers/infiniband/hw/irdma/
Ddefs.h1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
2 /* Copyright (c) 2015 - 2021 Intel Corporation */
123 ((IRDMA_QP_SW_MAX_WQ_QUANTA - IRDMA_SQ_RSVD) / (max_quanta_per_wr))
214 IRDMA_OP_CQ_MODIFY = 48,
360 (((u64)(val) << (dev)->hw_shifts[field ## _S]) & (dev)->hw_masks[field ## _M])
362 ((u64)((val) & (dev)->hw_masks[field ## _M]) >> (dev)->hw_shifts[field ## _S])
364 (((val) << (dev)->hw_shifts[field ## _S]) & (dev)->hw_masks[field ## _M])
366 ((u64)((val) & (dev)->hw_masks[field ## _M]) >> (dev)->hw_shifts[field ## _S])
409 #define IRDMA_CQPSQ_WS_VSI GENMASK_ULL(57, 48)
428 #define IRDMA_CQPHC_MIN_RATE GENMASK_ULL(51, 48)
[all …]
/linux-6.14.4/arch/parisc/kernel/
Dsignal32.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) 2001 Matthew Wilcox <willy at parisc-linux.org>
4 * Copyright (C) 2003 Carlos O'Donell <carlos at parisc-linux.org>
11 /* 32-bit ucontext as seen from an 64-bit kernel */
16 /* FIXME: Pad out to get uc_mcontext to start at an 8-byte aligned boundary */
24 /* In a deft move of uber-hackery, we decide to carry the top half of all
25 * 64-bit registers in a non-portable, non-ABI, hidden structure.
31 /* Upper half of all the 64-bit registers that were truncated
32 on a copy to a 32-bit userspace */
48 * The 32-bit ABI wants at least 48 bytes for a function call frame:
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