Lines Matching +full:48 +full:- +full:bit
2 // Accelerated CRC-T10DIF using ARM NEON and Crypto Extensions instructions
14 // Implement fast CRC-T10DIF computation with SSE and PCLMULQDQ instructions
62 // /white-papers/fast-crc-computation-generic-polynomials-pclmulqdq-paper.pdf
75 .arch armv8-a
76 .fpu crypto-neon-fp-armv8
116 * Pairwise long polynomial multiplication of two 16-bit values
120 * by two 64-bit values
125 * significant. The resulting 80-bit vectors are XOR'ed together.
139 * 6 (w0*x6 ^ w1*x5) << 48 ^ | (y0*z6 ^ y1*z5) << 48 ^
148 * and after performing 8x8->16 bit long polynomial multiplication of
150 * we obtain the following four vectors of 16-bit elements:
161 * final 80-bit result.
167 vtbl.8 d24, {\v16\()_L-\v16\()_H}, d24
168 vtbl.8 d25, {\v16\()_L-\v16\()_H}, d25
200 vld1.64 {q8-q9}, [buf]!
231 // the bit order match the polynomial coefficient order.
232 vld1.64 {q0-q1}, [buf]!
233 vld1.64 {q2-q3}, [buf]!
234 vld1.64 {q4-q5}, [buf]!
235 vld1.64 {q6-q7}, [buf]!
265 // While >= 128 data bytes remain (not counting q0-q7), fold the 128
266 // bytes q0-q7 into them, storing the result back into q0-q7.
275 // Now fold the 112 bytes in q0-q6 into the 16 bytes in q7.
293 adds len, len, #(128-16)
327 // q1 = high order part of second chunk: q7 left-shifted by 'len' bytes.
331 vtbl.8 q1l, {q7l-q7h}, q2l
332 vtbl.8 q1h, {q7l-q7h}, q2h
334 // q3 = first chunk: q7 right-shifted by '16-len' bytes.
337 vtbl.8 q3l, {q7l-q7h}, q2l
338 vtbl.8 q3h, {q7l-q7h}, q2h
340 // Convert to 8-bit masks: 'len' 0x00 bytes, then '16-len' 0xff bytes.
343 // q2 = second chunk: 'len' bytes from q0 (low-order bytes),
344 // then '16-len' bytes from q1 (high-order bytes).
367 // Load the fold-across-16-bytes constants.
388 // Reduce the 128-bit value M(x), stored in q7, to the final 16-bit CRC.
390 // Load 'x^48 * (x^48 mod G(x))' and 'x^48 * (x^80 mod G(x))'.
394 // x^64. This produces a 128-bit value congruent to x^64 * M(x) and
395 // whose low 48 bits are 0.
396 vmull.p64 q0, q7h, FOLD_CONST_H // high bits * x^48 * (x^80 mod G(x))
399 // Fold the high 32 bits into the low 96 bits. This produces a 96-bit
400 // value congruent to x^64 * M(x) and whose low 48 bits are 0.
404 vmull.p64 q1, q1l, FOLD_CONST_L // high 32 bits * x^48 * (x^48 mod G(x))
407 // Load G(x) and floor(x^48 / G(x)).
411 vmull.p64 q1, q0h, FOLD_CONST_H // high 32 bits * floor(x^48 / G(x))
414 vshr.u64 q0l, q0l, #48
452 .quad 0x1368000000000000 // x^48 * (x^48 mod G(x))
453 .quad 0x2d56000000000000 // x^48 * (x^80 mod G(x))
456 .quad 0x00000001f65a57f8 // floor(x^48 / G(x))
458 // For 1 <= len <= 15, the 16-byte vector beginning at &byteshift_table[16 -
460 // ..., 0x80} XOR the index vector to shift right by '16 - len' bytes.