Home
last modified time | relevance | path

Searched +full:32 +full:bit (Results 1 – 25 of 1514) sorted by relevance

12345678910>>...61

/linux-6.14.4/Documentation/devicetree/bindings/timer/
Drenesas,cmt.yaml14 The CMT is a multi-channel 16/32/48-bit timer/counter with configurable clock
28 - renesas,r8a7740-cmt0 # 32-bit CMT0 on R-Mobile A1
29 - renesas,r8a7740-cmt1 # 48-bit CMT1 on R-Mobile A1
30 - renesas,r8a7740-cmt2 # 32-bit CMT2 on R-Mobile A1
31 - renesas,r8a7740-cmt3 # 32-bit CMT3 on R-Mobile A1
32 - renesas,r8a7740-cmt4 # 32-bit CMT4 on R-Mobile A1
33 - renesas,sh73a0-cmt0 # 32-bit CMT0 on SH-Mobile AG5
34 - renesas,sh73a0-cmt1 # 48-bit CMT1 on SH-Mobile AG5
35 - renesas,sh73a0-cmt2 # 32-bit CMT2 on SH-Mobile AG5
36 - renesas,sh73a0-cmt3 # 32-bit CMT3 on SH-Mobile AG5
[all …]
/linux-6.14.4/Documentation/arch/arm64/
Dasymmetric-32bit.rst2 Asymmetric 32-bit SoCs
7 This document describes the impact of asymmetric 32-bit SoCs on the
8 execution of 32-bit (``AArch32``) applications.
16 of the CPUs are capable of executing 32-bit user applications. On such
19 ``execve(2)`` of 32-bit ELF binaries, with the latter returning
21 64-bit-only CPU, then the onlining operation fails and the new CPU is
25 running legacy 32-bit binaries. Unsurprisingly, that doesn't work very
28 It seems inevitable that future SoCs will drop 32-bit support
30 run 32-bit code on one of these transitionary platforms then you would
38 allowing 32-bit tasks to run on an asymmetric 32-bit system requires an
[all …]
/linux-6.14.4/drivers/net/fddi/skfp/h/
Dskfbi.h40 #define B0_RAP 0x0000 /* 8 bit register address port */
42 #define B0_CTRL 0x0004 /* 8 bit control register */
43 #define B0_DAS 0x0005 /* 8 Bit control register (DAS) */
44 #define B0_LED 0x0006 /* 8 Bit LED register */
45 #define B0_TST_CTRL 0x0007 /* 8 bit test control register */
46 #define B0_ISRC 0x0008 /* 32 bit Interrupt source register */
47 #define B0_IMSK 0x000c /* 32 bit Interrupt mask register */
52 #define B0_ST1U 0x0010 /* read upper 16-bit of status reg 1 */
53 #define B0_ST1L 0x0014 /* read lower 16-bit of status reg 1 */
54 #define B0_ST2U 0x0018 /* read upper 16-bit of status reg 2 */
[all …]
/linux-6.14.4/include/linux/
Dmath64.h16 * div_u64_rem - unsigned 64bit divide with 32bit divisor with remainder
17 * @dividend: unsigned 64bit dividend
18 * @divisor: unsigned 32bit divisor
19 * @remainder: pointer to unsigned 32bit remainder
23 * This is commonly provided by 32bit archs to provide an optimized 64bit
33 * div_s64_rem - signed 64bit divide with 32bit divisor with remainder
34 * @dividend: signed 64bit dividend
35 * @divisor: signed 32bit divisor
36 * @remainder: pointer to signed 32bit remainder
47 * div64_u64_rem - unsigned 64bit divide with 64bit divisor and remainder
[all …]
Dexportfs.h34 * 32bit inode number, 32 bit generation number.
39 * 32bit inode number, 32 bit generation number,
40 * 32 bit parent directory inode number.
45 * 64 bit object ID, 64 bit root object ID,
46 * 32 bit generation number.
51 * 64 bit object ID, 64 bit root object ID,
52 * 32 bit generation number,
53 * 64 bit parent object ID, 32 bit parent generation.
58 * 64 bit object ID, 64 bit root object ID,
59 * 32 bit generation number,
[all …]
Dnfs4.h110 OP_SAVEFH = 32,
436 FATTR4_MIMETYPE = 32,
519 * attribute bits within 32-bit word boundaries.
523 #define FATTR4_WORD0_SUPPORTED_ATTRS BIT(FATTR4_SUPPORTED_ATTRS)
524 #define FATTR4_WORD0_TYPE BIT(FATTR4_TYPE)
525 #define FATTR4_WORD0_FH_EXPIRE_TYPE BIT(FATTR4_FH_EXPIRE_TYPE)
526 #define FATTR4_WORD0_CHANGE BIT(FATTR4_CHANGE)
527 #define FATTR4_WORD0_SIZE BIT(FATTR4_SIZE)
528 #define FATTR4_WORD0_LINK_SUPPORT BIT(FATTR4_LINK_SUPPORT)
529 #define FATTR4_WORD0_SYMLINK_SUPPORT BIT(FATTR4_SYMLINK_SUPPORT)
[all …]
/linux-6.14.4/arch/s390/include/asm/
Delf.h13 #define R_390_8 1 /* Direct 8 bit. */
14 #define R_390_12 2 /* Direct 12 bit. */
15 #define R_390_16 3 /* Direct 16 bit. */
16 #define R_390_32 4 /* Direct 32 bit. */
17 #define R_390_PC32 5 /* PC relative 32 bit. */
18 #define R_390_GOT12 6 /* 12 bit GOT offset. */
19 #define R_390_GOT32 7 /* 32 bit GOT offset. */
20 #define R_390_PLT32 8 /* 32 bit PC relative PLT address. */
25 #define R_390_GOTOFF32 13 /* 32 bit offset to GOT. */
26 #define R_390_GOTPC 14 /* 32 bit PC rel. offset to GOT. */
[all …]
/linux-6.14.4/drivers/usb/typec/tipd/
Dtps6598x.h18 #define TPS_STATUS_PLUG_PRESENT BIT(0)
19 #define TPS_STATUS_PLUG_UPSIDE_DOWN BIT(4)
21 #define TPS_STATUS_PORTROLE BIT(5)
23 #define TPS_STATUS_DATAROLE BIT(6)
25 #define TPS_STATUS_VCONN BIT(7)
27 #define TPS_STATUS_OVERCURRENT BIT(16)
28 #define TPS_STATUS_GOTO_MIN_ACTIVE BIT(26)
29 #define TPS_STATUS_BIST BIT(27)
30 #define TPS_STATUS_HIGH_VOLAGE_WARNING BIT(28)
31 #define TPS_STATUS_HIGH_LOW_VOLTAGE_WARNING BIT(29)
[all …]
/linux-6.14.4/drivers/net/ethernet/marvell/
Dskge.h131 /* B0_CTST 16 bit Control/Status register */
138 CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
142 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
148 /* B0_LED 8 Bit LED register */
149 /* Bit 7.. 2: reserved */
153 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
164 /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
168 /* Bit 30: reserved */
215 /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
238 /* B2_TST_CTRL1 8 bit Test Control Register 1 */
[all …]
Dsky2.h41 PCI_PHY_LNK_TIM_MSK= 3L<<8,/* Bit 9.. 8: GPHY Link Trigger Timer */
48 PCI_VPD_WR_THR = 0xffL<<24, /* Bit 31..24: VPD Write Threshold */
49 PCI_DEV_SEL = 0x7fL<<17, /* Bit 23..17: EEPROM Device Select */
50 PCI_VPD_ROM_SZ = 7L<<14, /* Bit 16..14: VPD ROM Size */
52 PCI_PATCH_DIR = 0xfL<<8, /* Bit 11.. 8: Ext Patches dir 3..0 */
53 PCI_EXT_PATCHS = 0xfL<<4, /* Bit 7.. 4: Extended Patches 3..0 */
57 PCI_USEDATA64 = 1<<0, /* Use 64Bit Data bus ext */
60 /* PCI_OUR_REG_3 32 bit Our Register 3 (Yukon-ECU only) */
91 /* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */
94 P_PEX_LTSSM_STAT_MSK = 0x7fL<<25, /* Bit 31..25: PEX LTSSM Mask */
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/mfd/
Dmc13xxx.txt55 sw1a : regulator SW1A (register 24, bit 0)
56 sw1b : regulator SW1B (register 25, bit 0)
57 sw2a : regulator SW2A (register 26, bit 0)
58 sw2b : regulator SW2B (register 27, bit 0)
59 sw3 : regulator SW3 (register 29, bit 20)
60 vaudio : regulator VAUDIO (register 32, bit 0)
61 viohi : regulator VIOHI (register 32, bit 3)
62 violo : regulator VIOLO (register 32, bit 6)
63 vdig : regulator VDIG (register 32, bit 9)
64 vgen : regulator VGEN (register 32, bit 12)
[all …]
/linux-6.14.4/drivers/net/ethernet/cavium/liquidio/
Dcn66xx_regs.h89 /* 1 register (32-bit) to enable Input queues */
92 /* 1 register (32-bit) to enable Output queues */
95 /* 1 register (32-bit) to determine whether Output queues are in reset. */
98 /* 1 register (32-bit) to determine whether Input queues are in reset. */
103 /* 1 register (32-bit) - instr. size of each input queue. */
106 /* 32 registers for Input Queue Instr Count - SLI_PKT_IN_DONE0_CNTS */
109 /* 32 registers for Input Queue Start Addr - SLI_PKT0_INSTR_BADDR */
112 /* 32 registers for Input Doorbell - SLI_PKT0_INSTR_BAOFF_DBELL */
115 /* 32 registers for Input Queue size - SLI_PKT0_INSTR_FIFO_RSIZE */
118 /* 32 registers for Instruction Header Options - SLI_PKT0_INSTR_HEADER */
[all …]
/linux-6.14.4/arch/alpha/kernel/
Dsys_sable.c39 /* Note mask bit is true for DISABLED irqs. */
42 void (*update_irq_hw)(unsigned long bit, unsigned long mask);
43 void (*ack_irq_hw)(unsigned long bit);
64 * Bit Meaning Kernel IRQ
68 * 2 TULIP (builtin) 32
93 sable_update_irq_hw(unsigned long bit, unsigned long mask) in sable_update_irq_hw() argument
97 if (bit >= 16) { in sable_update_irq_hw()
100 } else if (bit >= 8) { in sable_update_irq_hw()
109 sable_ack_irq_hw(unsigned long bit) in sable_ack_irq_hw() argument
113 if (bit >= 16) { in sable_ack_irq_hw()
[all …]
/linux-6.14.4/lib/
Diomap_copy.c10 * __iowrite32_copy - copy data to MMIO space, in 32-bit units
11 * @to: destination, in MMIO space (must be 32-bit aligned)
12 * @from: source (must be 32-bit aligned)
13 * @count: number of 32-bit quantities to copy
15 * Copy data from kernel space to MMIO space, in units of 32 bits at a
33 * __ioread32_copy - copy data from MMIO space, in 32-bit units
34 * @to: destination (must be 32-bit aligned)
35 * @from: source, in MMIO space (must be 32-bit aligned)
36 * @count: number of 32-bit quantities to copy
38 * Copy data from MMIO space to kernel space, in units of 32 bits at a
[all …]
/linux-6.14.4/drivers/staging/media/ipu3/
Dipu3-abi.h15 #define IMGU_DVS_BLOCK_H 32
31 #define IMGU_ABI_AF_MAX_CELLS_PER_SET 32
32 #define IMGU_ABI_AWB_FR_MAX_CELLS_PER_SET 32
46 #define IMGU_PM_CTRL_START BIT(0)
47 #define IMGU_PM_CTRL_CFG_DONE BIT(1)
48 #define IMGU_PM_CTRL_RACE_TO_HALT BIT(2)
49 #define IMGU_PM_CTRL_NACK_ALL BIT(3)
50 #define IMGU_PM_CTRL_CSS_PWRDN BIT(4)
51 #define IMGU_PM_CTRL_RST_AT_EOF BIT(5)
52 #define IMGU_PM_CTRL_FORCE_HALT BIT(6)
[all …]
/linux-6.14.4/include/uapi/linux/
Dswab.h71 __u32 h = val >> 32; in __fswab64()
72 __u32 l = val & ((1ULL << 32) - 1); in __fswab64()
73 return (((__u64)__fswab32(l)) << 32) | ((__u64)(__fswab32(h))); in __fswab64()
98 * __swab16 - return a byteswapped 16-bit value
111 * __swab32 - return a byteswapped 32-bit value
124 * __swab64 - return a byteswapped 64-bit value
140 #else /* __BITS_PER_LONG == 32 */ in __swab()
146 * __swahw32 - return a word-swapped 32-bit value
157 * __swahb32 - return a high and low byte-swapped 32-bit value
168 * __swab16p - return a byteswapped 16-bit value from a pointer
[all …]
/linux-6.14.4/fs/ext4/
Dinode-test.c43 "1901-12-13 Lower bound of 32bit < 0 timestamp, no extra bits"
45 "1969-12-31 Upper bound of 32bit < 0 timestamp, no extra bits"
47 "1970-01-01 Lower bound of 32bit >=0 timestamp, no extra bits"
49 "2038-01-19 Upper bound of 32bit >=0 timestamp, no extra bits"
51 "2038-01-19 Lower bound of 32bit <0 timestamp, lo extra sec bit on"
53 "2106-02-07 Upper bound of 32bit <0 timestamp, lo extra sec bit on"
55 "2106-02-07 Lower bound of 32bit >=0 timestamp, lo extra sec bit on"
57 "2174-02-25 Upper bound of 32bit >=0 timestamp, lo extra sec bit on"
59 "2174-02-25 Lower bound of 32bit <0 timestamp, hi extra sec bit on"
61 "2242-03-16 Upper bound of 32bit <0 timestamp, hi extra sec bit on"
[all …]
/linux-6.14.4/Documentation/admin-guide/
Dhighuid.rst2 Notes on the change from 16-bit UIDs to 32-bit UIDs
15 What's left to be done for 32-bit UIDs on all Linux architectures:
22 properly with huge UIDs. If it can deal with 64-bit file offsets on all
27 (currently, the old 16-bit UID and GID are still written to disk, and
28 part of the former pad space is used to store separate 32-bit UID and
31 - Need to validate that OS emulation calls the 16-bit UID
32 compatibility syscalls, if the OS being emulated used 16-bit UIDs, or
33 uses the 32-bit UID system calls properly otherwise.
40 (need to support whatever new 32-bit UID system calls are added to
45 At present, 32-bit UIDs _should_ work for:
[all …]
/linux-6.14.4/Documentation/staging/
Dcrc32.rst17 subtract, we just xor. Thus, we tend to get a bit sloppy about
21 To produce a 32-bit CRC, the divisor is actually a 33-bit CRC polynomial.
22 Since it's 33 bits long, bit 32 is always going to be set, so usually the
23 CRC is written in hex with the most significant bit omitted. (If you're
30 little-endian; the most significant bit (sometimes used for parity)
34 Just like with ordinary division, you proceed one digit (bit) at a time.
35 Each step of the division you take one more digit (bit) of the dividend
39 and to make the XOR cancel, it's just a copy of bit 32 of the remainder.
42 throw the quotient bit away, but subtract the appropriate multiple of
44 ready to process the next bit.
[all …]
/linux-6.14.4/arch/s390/kernel/
Dmodule.c63 case R_390_GOT12: /* 12 bit GOT offset. */ in check_rela()
64 case R_390_GOT16: /* 16 bit GOT offset. */ in check_rela()
65 case R_390_GOT20: /* 20 bit GOT offset. */ in check_rela()
66 case R_390_GOT32: /* 32 bit GOT offset. */ in check_rela()
67 case R_390_GOT64: /* 64 bit GOT offset. */ in check_rela()
68 case R_390_GOTENT: /* 32 bit PC rel. to GOT entry shifted by 1. */ in check_rela()
69 case R_390_GOTPLT12: /* 12 bit offset to jump slot. */ in check_rela()
70 case R_390_GOTPLT16: /* 16 bit offset to jump slot. */ in check_rela()
71 case R_390_GOTPLT20: /* 20 bit offset to jump slot. */ in check_rela()
72 case R_390_GOTPLT32: /* 32 bit offset to jump slot. */ in check_rela()
[all …]
/linux-6.14.4/tools/testing/selftests/powerpc/vphn/
Dtest-vphn.c41 "vphn: 1 x 16-bit value",
56 "vphn: 2 x 16-bit values",
72 "vphn: 3 x 16-bit values",
89 "vphn: 4 x 16-bit values",
107 /* Parsing the next 16-bit value out of the next 64-bit input
110 "vphn: 5 x 16-bit values",
129 /* Parse at most 6 x 64-bit input values */
130 "vphn: 24 x 16-bit values",
168 "vphn: 1 x 32-bit value",
183 "vphn: 2 x 32-bit values",
[all …]
/linux-6.14.4/lib/math/
Ddiv64.c10 * Generic C version of 64bit/32bit division and modulo, with
11 * 64bit result and 32bit remainder.
13 * The fast case for (n>>32 == 0) is handled inline by do_div().
28 /* Not needed on 64bit architectures */
29 #if BITS_PER_LONG == 32
37 uint32_t high = rem >> 32; in __div64_32()
39 /* Reduce the thing a bit first */ in __div64_32()
43 res = (uint64_t) high << 32; in __div64_32()
44 rem -= (uint64_t) (high*base) << 32; in __div64_32()
88 * div64_u64_rem - unsigned 64bit divide with 64bit divisor and remainder
[all …]
/linux-6.14.4/arch/arm64/include/asm/
Dkgdb.h34 * r0-r30: 64 bit
35 * sp,pc : 64 bit
36 * pstate : 32 bit
39 * f0-f31: 128 bit
40 * fpsr & fpcr: 32 bit
41 * Total: 32 + 2
45 * Architecture Reference Manual that claimed "SPSR_ELx is a 32-bit register".
46 * and, as a result, allocated only 32-bits for the PSTATE in the remote
49 * Unfortunately "is a 32-bit register" has a very special meaning for
50 * system registers. It means that "the upper bits, bits[63:32], are
[all …]
/linux-6.14.4/drivers/gpu/drm/i915/gvt/
Dfb_decoder.c56 {DRM_FORMAT_C8, 8, "8-bit Indexed"},
57 {DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"},
58 {DRM_FORMAT_XRGB8888, 32, "32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"},
59 {DRM_FORMAT_XBGR2101010, 32, "32-bit RGBX (2:10:10:10 MSB-X:B:G:R)"},
61 {DRM_FORMAT_XRGB2101010, 32, "32-bit BGRX (2:10:10:10 MSB-X:R:G:B)"},
62 {DRM_FORMAT_XBGR8888, 32, "32-bit RGBX (8:8:8:8 MSB-X:B:G:R)"},
69 {DRM_FORMAT_YUYV, 16, "16-bit packed YUYV (8:8:8:8 MSB-V:Y2:U:Y1)"},
70 {DRM_FORMAT_UYVY, 16, "16-bit packed UYVY (8:8:8:8 MSB-Y2:V:Y1:U)"},
71 {DRM_FORMAT_YVYU, 16, "16-bit packed YVYU (8:8:8:8 MSB-U:Y2:V:Y1)"},
72 {DRM_FORMAT_VYUY, 16, "16-bit packed VYUY (8:8:8:8 MSB-Y2:U:Y1:V)"},
[all …]
/linux-6.14.4/drivers/acpi/acpica/
Dtbfadt.c166 * Bit width field in the GAS is only one byte long, 255 max. in acpi_tb_init_generic_address()
170 if (byte_width > 31) { /* (31*8)=248, (32*8)=256 */ in acpi_tb_init_generic_address()
178 "%s - 32-bit FADT register is too long (%u bytes, %u bits) " in acpi_tb_init_generic_address()
188 * The 64-bit Address field is non-aligned in the byte packed in acpi_tb_init_generic_address()
206 * address32 - 32-bit address of the register
207 * address64 - 64-bit address of the register
209 * RETURN: The resolved 64-bit address
211 * DESCRIPTION: Select between 32-bit and 64-bit versions of addresses within
217 * the 32-bit and 64-bit address fields (FIRMWARE_CTRL/X_FIRMWARE_CTRL and
222 * By default, as per the ACPICA specification, a valid 64-bit address is
[all …]

12345678910>>...61