Lines Matching +full:32 +full:bit
89 /* 1 register (32-bit) to enable Input queues */
92 /* 1 register (32-bit) to enable Output queues */
95 /* 1 register (32-bit) to determine whether Output queues are in reset. */
98 /* 1 register (32-bit) to determine whether Input queues are in reset. */
103 /* 1 register (32-bit) - instr. size of each input queue. */
106 /* 32 registers for Input Queue Instr Count - SLI_PKT_IN_DONE0_CNTS */
109 /* 32 registers for Input Queue Start Addr - SLI_PKT0_INSTR_BADDR */
112 /* 32 registers for Input Doorbell - SLI_PKT0_INSTR_BAOFF_DBELL */
115 /* 32 registers for Input Queue size - SLI_PKT0_INSTR_FIFO_RSIZE */
118 /* 32 registers for Instruction Header Options - SLI_PKT0_INSTR_HEADER */
121 /* 1 register (64-bit) - Back Pressure for each input queue - SLI_PKT0_IN_BP */
127 /* 1 register (32-bit) - ES, RO, NS, Arbitration for Input Queue Data &
132 /* 1 register (64-bit) - Number of instructions to read at one time
137 /* 1 register (64-bit) - Assign Input ring to MAC port
162 #define CN6XXX_INPUT_CTL_ROUND_ROBIN_ARB BIT(22)
163 #define CN6XXX_INPUT_CTL_DATA_NS BIT(8)
164 #define CN6XXX_INPUT_CTL_DATA_ES_64B_SWAP BIT(6)
165 #define CN6XXX_INPUT_CTL_DATA_RO BIT(5)
166 #define CN6XXX_INPUT_CTL_USE_CSR BIT(4)
167 #define CN6XXX_INPUT_CTL_GATHER_NS BIT(3)
168 #define CN6XXX_INPUT_CTL_GATHER_ES_64B_SWAP BIT(2)
169 #define CN6XXX_INPUT_CTL_GATHER_RO BIT(1)
184 /* 32 registers for Output queue buffer and info size - SLI_PKT0_OUT_SIZE */
187 /* 32 registers for Output Queue Start Addr - SLI_PKT0_SLIST_BADDR */
190 /* 32 registers for Output Queue Packet Credits - SLI_PKT0_SLIST_BAOFF_DBELL */
193 /* 32 registers for Output Queue size - SLI_PKT0_SLIST_FIFO_RSIZE */
196 /* 32 registers for Output Queue Packet Count - SLI_PKT0_CNTS */
202 /* 1 register (32-bit) - 1 bit for each output queue
208 /* 1 register (32-bit) - 1 bit for each output queue
214 /* 1 register (64-bit) - 2 bits for each output queue
220 /* 1 register (32-bit) - 1 bit for each output queue
226 /* 1 register (32-bit) - 1 bit for each output queue
232 /* 1 register (32-bit) - 1 bit for each output queue
238 /* 1 register (32-bit) - 1 bit for each output queue
244 /* 1 register (64-bit) - 2 bits for each output queue
250 /* 1 register (32-bit) - 1 bit for each output queue
256 /* 1 register (64-bit) - 2 bits for each output queue
262 /* 1 (64-bit) register for Output Queue Packet Count Interrupt Threshold
263 * & Time Threshold. The same setting applies to all 32 queues.
264 * The register is defined as a 64-bit registers, but we use the
265 * 32-bit offsets to define distinct addresses.
270 /* 1 (64-bit register) for Output Queue backpressure across all rings. */
294 /* 2 registers (64-bit) - DMA Count - 1 for each DMA counter 0/1. */
297 /* 2 registers (64-bit) - DMA Timer 0/1, contains DMA timer values
302 /* 2 registers (64-bit) - DMA count & Time Interrupt threshold -
328 /* 1 register (64-bit) for Interrupt Summary */
331 /* 1 register (64-bit) for Interrupt Enable */
335 /* 1 register (32-bit) to enable Output Queue Packet/Byte Count Interrupt */
338 /* 1 register (32-bit) to enable Output Queue Packet Timer Interrupt */
341 /* 1 register (32-bit) to indicate which Output Queue reached pkt threshold */
344 /* 1 register (32-bit) to indicate which Output Queue reached time threshold */
349 #define CN6XXX_INTR_RML_TIMEOUT_ERR BIT(1)
350 #define CN6XXX_INTR_BAR0_RW_TIMEOUT_ERR BIT(2)
351 #define CN6XXX_INTR_IO2BIG_ERR BIT(3)
352 #define CN6XXX_INTR_PKT_COUNT BIT(4)
353 #define CN6XXX_INTR_PKT_TIME BIT(5)
354 #define CN6XXX_INTR_M0UPB0_ERR BIT(8)
355 #define CN6XXX_INTR_M0UPWI_ERR BIT(9)
356 #define CN6XXX_INTR_M0UNB0_ERR BIT(10)
357 #define CN6XXX_INTR_M0UNWI_ERR BIT(11)
358 #define CN6XXX_INTR_M1UPB0_ERR BIT(12)
359 #define CN6XXX_INTR_M1UPWI_ERR BIT(13)
360 #define CN6XXX_INTR_M1UNB0_ERR BIT(14)
361 #define CN6XXX_INTR_M1UNWI_ERR BIT(15)
362 #define CN6XXX_INTR_MIO_INT0 BIT(16)
363 #define CN6XXX_INTR_MIO_INT1 BIT(17)
364 #define CN6XXX_INTR_MAC_INT0 BIT(18)
365 #define CN6XXX_INTR_MAC_INT1 BIT(19)
367 #define CN6XXX_INTR_DMA0_FORCE BIT_ULL(32)