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/linux-6.14.4/Documentation/devicetree/bindings/powerpc/fsl/
Dmpic.txt14 - compatible
22 - reg
24 Value type: <prop-encoded-array>
29 - interrupt-controller
35 - #interrupt-cells
39 specifiers do not contain the interrupt-type or type-specific
42 - #address-cells
47 - pic-no-reset
53 configuration registers to a sane state-- masked or
60 - big-endian
[all …]
Dmpc5200.txt2 ----------------------------
4 (c) 2006-2009 Secret Lab Technologies Ltd
8 ------------------
9 For mpc5200 on-chip devices, the format for each compatible value is
10 <chip>-<device>[-<mode>]. The OS should be able to match a device driver
21 "fsl,mpc5200-<device>".
29 compatible = "fsl,mpc5200b-<device>","fsl,mpc5200-<device>";
34 ie. ethernet on mpc5200: compatible = "fsl,mpc5200-fec";
35 ethernet on mpc5200b: compatible = "fsl,mpc5200b-fec", "fsl,mpc5200-fec";
39 "fsl,mpc5200-psc-i2s", not "fsl,mpc5200-i2s". This convention is chosen to
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/linux-6.14.4/Documentation/devicetree/bindings/clock/
Dstericsson,u8500-clks.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/stericsson,u8500-clks.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson DB8500 (U8500) clocks
10 - Ulf Hansson <[email protected]>
11 - Linus Walleij <[email protected]>
14 DB8500 digital baseband system-on-chip and its siblings such as
16 itself, not off-chip clocks. There are four different on-chip
17 clocks - RTC (32 kHz), CPU clock (SMP TWD), PRCMU (power reset and
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/linux-6.14.4/fs/afs/
Dproc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
37 struct afs_cell *cell; in afs_proc_cells_show() local
45 cell = list_entry(v, struct afs_cell, proc_link); in afs_proc_cells_show()
46 vllist = rcu_dereference(cell->vl_servers); in afs_proc_cells_show()
48 /* display one cell per line on subsequent lines */ in afs_proc_cells_show()
49 seq_printf(m, "%3u %3u %6lld %2u %2u %s\n", in afs_proc_cells_show()
50 refcount_read(&cell->ref), in afs_proc_cells_show()
51 atomic_read(&cell->active), in afs_proc_cells_show()
52 cell->dns_expiry - ktime_get_real_seconds(), in afs_proc_cells_show()
53 vllist ? vllist->nr_servers : 0, in afs_proc_cells_show()
[all …]
Ddynroot.c1 // SPDX-License-Identifier: GPL-2.0-or-later
30 struct afs_super_info *as = AFS_FS_S(inode->i_sb); in afs_iget5_pseudo_set()
34 vnode->volume = as->volume; in afs_iget5_pseudo_set()
35 vnode->fid = *fid; in afs_iget5_pseudo_set()
36 inode->i_ino = fid->vnode; in afs_iget5_pseudo_set()
37 inode->i_generation = fid->unique; in afs_iget5_pseudo_set()
54 if (as->volume) in afs_iget_pseudo_dir()
55 fid.vid = as->volume->vid; in afs_iget_pseudo_dir()
67 _leave(" = -ENOMEM"); in afs_iget_pseudo_dir()
68 return ERR_PTR(-ENOMEM); in afs_iget_pseudo_dir()
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/linux-6.14.4/arch/powerpc/boot/dts/fsl/
Dt4240si-post.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10000 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10000 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10000 0>;
51 #address-cells = <2>;
52 #size-cells = <1>;
59 compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
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Dqoriq-fman-1.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 #address-cells = <1>;
37 #size-cells = <1>;
38 cell-index = <1>;
43 clocks = <&clockgen 3 1>;
44 clock-names = "fmanclk";
45 fsl,qman-channel-range = <0x60 0xc>;
46 ptimer-handle = <&ptp_timer1>;
49 compatible = "fsl,fman-muram";
54 cell-index = <0x1>;
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Dqoriq-fman-0.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 #address-cells = <1>;
37 #size-cells = <1>;
38 cell-index = <0>;
43 clocks = <&clockgen 3 0>;
44 clock-names = "fmanclk";
45 fsl,qman-channel-range = <0x40 0xc>;
46 ptimer-handle = <&ptp_timer0>;
49 compatible = "fsl,fman-muram";
54 cell-index = <0x1>;
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/linux-6.14.4/arch/arm64/boot/dts/freescale/
Dqoriq-qman-portals.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
5 * Copyright 2011-2016 Freescale Semiconductor Inc.
10 #address-cells = <1>;
11 #size-cells = <1>;
12 compatible = "simple-bus";
14 qportal0: qman-portal@0 {
16 * bootloader fix-ups are expected to provide the
17 * "fsl,bman-portal-<hardware revision>" compatible
19 compatible = "fsl,qman-portal";
22 cell-index = <0>;
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/linux-6.14.4/Documentation/devicetree/bindings/mips/cavium/
Dbootbus.txt7 - compatible: "cavium,octeon-3860-bootbus"
11 - reg: The base address of the Boot Bus' register bank.
13 - #address-cells: Must be <2>. The first cell is the chip select
14 within the bootbus. The second cell is the offset from the chip select.
16 - #size-cells: Must be <1>.
18 - ranges: There must be one one triplet of (child-bus-address,
19 parent-bus-address, length) for each active chip select. If the
27 - compatible: "cavium,octeon-3860-bootbus-config"
29 - cavium,cs-index: A single cell indicating the chip select that
32 - cavium,t-adr: A cell specifying the ADR timing (in nS).
[all …]
/linux-6.14.4/arch/powerpc/boot/dts/
Dfsp2.dts12 /dts-v1/;
15 #address-cells = <2>;
16 #size-cells = <1>;
19 dcr-parent = <&{/cpus/cpu@0}>;
28 #address-cells = <1>;
29 #size-cells = <0>;
35 clock-frequency = <0>; /* Filled in by cuboot */
36 timebase-frequency = <0>; /* Filled in by cuboot */
37 i-cache-line-size = <32>;
38 d-cache-line-size = <32>;
[all …]
Dmpc832x_rdb.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
25 #address-cells = <1>;
26 #size-cells = <0>;
31 d-cache-line-size = <0x20>; // 32 bytes
32 i-cache-line-size = <0x20>; // 32 bytes
33 d-cache-size = <16384>; // L1, 16K
34 i-cache-size = <16384>; // L1, 16K
[all …]
Dmpc8377_wlan.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2007-2009 Freescale Semiconductor Inc.
9 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
27 #address-cells = <1>;
28 #size-cells = <0>;
33 d-cache-line-size = <32>;
34 i-cache-line-size = <32>;
35 d-cache-size = <32768>;
[all …]
Dxpedite5200.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
29 #address-cells = <1>;
30 #size-cells = <0>;
35 d-cache-line-size = <32>; // 32 bytes
36 i-cache-line-size = <32>; // 32 bytes
37 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <0x8000>; // L1, 32K
[all …]
Dtqm8548.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
9 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
30 #address-cells = <1>;
31 #size-cells = <0>;
36 d-cache-line-size = <32>; // 32 bytes
37 i-cache-line-size = <32>; // 32 bytes
38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
[all …]
Dtqm8548-bigflash.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
9 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
30 #address-cells = <1>;
31 #size-cells = <0>;
36 d-cache-line-size = <32>; // 32 bytes
37 i-cache-line-size = <32>; // 32 bytes
38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
[all …]
Dxpedite5200_xmon.dts1 // SPDX-License-Identifier: GPL-2.0-only
7 * xMon boot loader memory map which differs from U-Boot's.
10 /dts-v1/;
15 #address-cells = <1>;
16 #size-cells = <1>;
17 form-factor = "PMC/XMC";
18 boot-bank = <0x0>;
33 #address-cells = <1>;
34 #size-cells = <0>;
39 d-cache-line-size = <32>; // 32 bytes
[all …]
Dtqm8540.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
15 #address-cells = <1>;
16 #size-cells = <1>;
28 #address-cells = <1>;
29 #size-cells = <0>;
34 d-cache-line-size = <32>;
35 i-cache-line-size = <32>;
36 d-cache-size = <32768>;
37 i-cache-size = <32768>;
[all …]
Dmpc836x_rdk.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright 2007-2008 MontaVista Software, Inc.
11 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
31 #address-cells = <1>;
32 #size-cells = <0>;
37 d-cache-line-size = <32>;
38 i-cache-line-size = <32>;
39 d-cache-size = <32768>;
[all …]
Dmpc8315erdb.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
12 #address-cells = <1>;
13 #size-cells = <1>;
26 #address-cells = <1>;
27 #size-cells = <0>;
32 d-cache-line-size = <32>;
33 i-cache-line-size = <32>;
34 d-cache-size = <16384>;
35 i-cache-size = <16384>;
[all …]
Dxcalibur1501.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 * XCalibur1501 6U CompactPCI single-board computer based on MPC8572E
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
27 #address-cells = <1>;
28 #size-cells = <0>;
33 d-cache-line-size = <32>; // 32 bytes
34 i-cache-line-size = <32>; // 32 bytes
35 d-cache-size = <0x8000>; // L1, 32K
[all …]
/linux-6.14.4/include/uapi/linux/
Datm.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2 /* atm.h - general ATM declarations */
4 /* Written 1995-2000 by Werner Almesberger, EPFL LRC/ICA */
8 * WARNING: User-space programs should not #include <linux/atm.h> directly.
28 #define ATM_CELL_SIZE 53 /* ATM cell size incl. header */
35 #define ATM_NOT_RSV_VCI 32 /* first non-reserved VCI value */
47 #define ATM_AAL34 3 /* AAL3/4 (data) */
69 /* set CLP bit value - TODO */
75 #define SO_ATMSAP __SO_ENCODE(SOL_ATM,3,struct atm_sap)
85 * the data plane but generally seems to be data plane-centric, any layer is
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/linux-6.14.4/Documentation/devicetree/bindings/reset/
Dti-syscon-reset.txt6 typically provided by means of memory-mapped I/O registers. These registers are
22 --------------------
23 - compatible : Should be,
24 "ti,k2e-pscrst"
25 "ti,k2l-pscrst"
26 "ti,k2hk-pscrst"
27 "ti,syscon-reset"
28 - #reset-cells : Should be 1. Please see the reset consumer node below
30 - ti,reset-bits : Contains the reset control register information
33 Cell #1 : offset of the reset assert control
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/mailbox/
Dbrcm,iproc-flexrm-mbox.txt6 FlexRM driver will create a mailbox-controller instance for given FlexRM
10 --------------------
11 - compatible: Should be "brcm,iproc-flexrm-mbox"
12 - reg: Specifies base physical address and size of the FlexRM
14 - msi-parent: Phandles (and potential Device IDs) to MSI controllers
17 Refer devicetree/bindings/interrupt-controller/msi.txt
18 - #mbox-cells: Specifies the number of cells needed to encode a mailbox
19 channel. This should be 3.
21 The 1st cell is the mailbox channel number.
23 The 2nd cell contains MSI completion threshold. This is the
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/powerpc/4xx/
Dcpm.txt4 - compatible : compatible list, currently only "ibm,cpm"
5 - dcr-access-method : "native"
6 - dcr-reg : < DCR register range >
9 - er-offset : All 4xx SoCs with a CPM controller have
15 er-offset = <1>.
16 - unused-units : specifier consist of one cell. For each
17 bit in the cell, the corresponding bit
20 - idle-doze : specifier consist of one cell. For each
21 bit in the cell, the corresponding bit
24 - standby : specifier consist of one cell. For each
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