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/linux-6.14.4/Documentation/devicetree/bindings/phy/
Dmicrochip,sparx5-serdes.yaml36 * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
37 * 3.125 Gbps (2.5GBASE-X/2.5GBASE-KX)
38 * 5.15625 Gbps (5GBASE-KR/5G-USXGMII)
46 * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
47 * 3.125 Gbps (2.5GBASE-X/2.5GBASE-KX)
48 * 5 Gbps (QSGMII/USGMII)
49 * 5.15625 Gbps (5GBASE-KR/5G-USXGMII)
50 * 10 Gbps (10G-USGMII)
51 * 10.3125 Gbps (10GBASE-R/10GBASE-KR/USXGMII)
58 * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
[all …]
Dapm-xgene-phy.txt1 * APM X-Gene 15Gbps Multi-purpose PHY nodes
3 PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each
9 - #phy-cells : Shall be 1 as it expects one argument for setting
11 1 (SGMII), 2 (PCIe), 3 (USB), and 4 (XFI).
23 data earlier than the nominal sampling point. 1 means
35 - apm,tx-pre-cursor1 : 1st pre-cursor emphasis taps control. Two set of
48 0 = 1-2Gbps
49 1 = 2-4Gbps (1st tuple default)
50 2 = 4-8Gbps
51 3 = 8-15Gbps (2nd tuple default)
[all …]
Dmediatek,hdmi-phy.yaml34 maxItems: 1
56 TX DRV bias current for < 1.65Gbps
64 TX DRV bias current for >= 1.65Gbps
/linux-6.14.4/drivers/scsi/mvsas/
Dmv_94xx.h72 /* ports 1-3 follow after this */
79 /* ports 1-3 follow after this */
84 /* ports 1-3 follow after this */
91 /* phys 1-3 follow after this */
94 /* phys 1-3 follow after this */
117 VSR_PHY_MODE5 = 0x05 * 4, /* Phy Counter 1 */
121 VSR_PHY_MODE9 = 0x09 * 4, /* Event Counter 1 */
141 MVS_IRQ_COM_IN_I2O_IOP0 = (1 << 0),
142 MVS_IRQ_COM_IN_I2O_IOP1 = (1 << 1),
143 MVS_IRQ_COM_IN_I2O_IOP2 = (1 << 2),
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/media/i2c/
Dmaxim,max96712.yaml21 Each GMSL2 serial link operates at a fixed rate of 3Gbps or 6Gbps in the
23 MAX96712 can be paired with first-generation 3.12Gbps or 1.5Gbps GMSL1
24 serializers or operate up to 3.12Gbps with GMSL2 serializers in GMSL1 mode.
35 maxItems: 1
47 port@1:
49 description: GMSL Input 1
73 - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
96 #address-cells = <1>;
107 #address-cells = <1>;
115 data-lanes = <1 2 3 4>;
Dmaxim,max96717.yaml25 The GMSL2 serial link operates at a fixed rate of 3Gbps or 6Gbps in the
27 MAX96717F only supports a fixed rate of 3Gbps in the forward direction.
50 maxItems: 1
68 minItems: 1
72 minItems: 1
78 port@1:
84 - port@1
107 #address-cells = <1>;
117 #address-cells = <1>;
123 data-lanes = <1 2 3 4>;
[all …]
Dmaxim,max96714.yaml23 The GMSL2 serial link operates at a fixed rate of 3Gbps or 6Gbps in the
25 MAX96714F only supports a fixed rate of 3Gbps in the forward direction.
37 maxItems: 1
40 maxItems: 1
59 port@1:
71 minItems: 1
75 minItems: 1
79 maxItems: 1
85 - port@1
111 #address-cells = <1>;
[all …]
Dovti,ov08x40.yaml19 - 4-lane MIPI D-PHY TX @ 1 Gbps per lane
20 - 2-lane MPIP D-PHY TX @ 2 Gbps per lane
32 maxItems: 1
35 maxItems: 1
62 - const: 1
65 - const: 1
90 #address-cells = <1>;
114 data-lanes = <1 2 3 4>;
/linux-6.14.4/drivers/scsi/bfa/
Dbfad_attr.c28 u32 fc_id = -1; in bfad_im_get_starget_port_id()
193 fc_host_active_fc4s(shost)[2] = 1; in bfad_im_get_host_active_fc4s()
195 fc_host_active_fc4s(shost)[7] = 1; in bfad_im_get_host_active_fc4s()
335 * In case it is lesser than path_tov of driver, set it to path_tov + 1
348 rport->dev_loss_tmo = path_tov + 1; in bfad_im_set_rport_loss_tmo()
414 fc_host_supported_fc4s(vshost)[2] = 1; in bfad_im_vport_create()
417 fc_host_supported_fc4s(vshost)[7] = 1; in bfad_im_vport_create()
520 return -1; in bfad_im_vport_delete()
597 .show_starget_port_id = 1,
599 .show_starget_node_name = 1,
[all …]
/linux-6.14.4/drivers/gpu/drm/amd/display/dc/
Ddc_dp_types.h34 LANE_COUNT_ONE = 1,
50 LINK_RATE_LOW = 0x06, // Rate_1 (RBR) - 1.62 Gbps/Lane
51 LINK_RATE_RATE_2 = 0x08, // Rate_2 - 2.16 Gbps/Lane
52 LINK_RATE_RATE_3 = 0x09, // Rate_3 - 2.43 Gbps/Lane
53 LINK_RATE_HIGH = 0x0A, // Rate_4 (HBR) - 2.70 Gbps/Lane
54 LINK_RATE_RBR2 = 0x0C, // Rate_5 (RBR2) - 3.24 Gbps/Lane
55 LINK_RATE_RATE_6 = 0x10, // Rate_6 - 4.32 Gbps/Lane
56 LINK_RATE_HIGH2 = 0x14, // Rate_7 (HBR2) - 5.40 Gbps/Lane
57 LINK_RATE_RATE_8 = 0x19, // Rate_8 - 6.75 Gbps/Lane
58 LINK_RATE_HIGH3 = 0x1E, // Rate_9 (HBR3) - 8.10 Gbps/Lane
[all …]
/linux-6.14.4/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
Dsmu11_driver_if_arcturus.h44 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)
45 #define MAX_VCLK_DPM_LEVEL (NUM_VCLK_DPM_LEVELS - 1)
46 #define MAX_DCLK_DPM_LEVEL (NUM_DCLK_DPM_LEVELS - 1)
47 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
48 #define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1)
49 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1)
50 #define MAX_FCLK_DPM_LEVEL (NUM_FCLK_DPM_LEVELS - 1)
51 #define MAX_XGMI_LEVEL (NUM_XGMI_LEVELS - 1)
52 #define MAX_XGMI_PSTATE_LEVEL (NUM_XGMI_PSTATE_LEVELS - 1)
57 #define FEATURE_DPM_GFXCLK_BIT 1
[all …]
Dsmu11_driver_if_sienna_cichlid.h53 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)
54 #define MAX_SMNCLK_DPM_LEVEL (NUM_SMNCLK_DPM_LEVELS - 1)
55 #define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1)
56 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
57 #define MAX_DCLK_DPM_LEVEL (NUM_DCLK_DPM_LEVELS - 1)
58 #define MAX_VCLK_DPM_LEVEL (NUM_VCLK_DPM_LEVELS - 1)
59 #define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
60 #define MAX_DISPCLK_DPM_LEVEL (NUM_DISPCLK_DPM_LEVELS - 1)
61 #define MAX_PIXCLK_DPM_LEVEL (NUM_PIXCLK_DPM_LEVELS - 1)
62 #define MAX_PHYCLK_DPM_LEVEL (NUM_PHYCLK_DPM_LEVELS - 1)
[all …]
/linux-6.14.4/drivers/net/ethernet/ezchip/
Dnps_enet.h19 #define NPS_ENET_ENABLE 1
57 #define TX_DONE_SHIFT 1
59 /* Gbps Eth MAC Configuration 0 register masks and shifts */
63 #define CFG_0_TX_EN_SHIFT 1
93 /* Gbps Eth MAC Configuration 1 register masks and shifts */
103 /* Gbps Eth MAC Configuration 2 register masks and shifts */
119 /* Gbps Eth MAC Configuration 3 register masks and shifts */
123 #define CFG_3_RX_CBFC_EN_SHIFT 1
151 #define PHASE_FIFO_CTL_INIT_SHIFT 1
/linux-6.14.4/drivers/gpu/drm/meson/
Dmeson_dw_hdmi.c120 MESON_VENC_SOURCE_ENCI = 1,
291 /* 5.94Gbps, 3.7125Gbps */ in meson_hdmi_phy_setup_mode()
295 /* 2.97Gbps */ in meson_hdmi_phy_setup_mode()
299 /* 1.485Gbps */ in meson_hdmi_phy_setup_mode()
310 /* 5.94Gbps, 3.7125Gbps */ in meson_hdmi_phy_setup_mode()
314 /* 2.97Gbps */ in meson_hdmi_phy_setup_mode()
318 /* 1.485Gbps, and below */ in meson_hdmi_phy_setup_mode()
325 /* 5.94Gbps, 3.7125Gbps */ in meson_hdmi_phy_setup_mode()
330 /* 2.97Gbps */ in meson_hdmi_phy_setup_mode()
335 /* 1.485Gbps, and below */ in meson_hdmi_phy_setup_mode()
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/net/
Dmicrochip,sparx5-switch.yaml31 1G/2.5G/5G/10G switching with 10G/25G aggregation links is required.
70 minItems: 1
77 minItems: 1
99 const: 1
113 maxItems: 1
135 the DLL phase shift between 1000 ps (45 degree shift at 1Gbps) and
136 3300 ps (147 degree shift at 1Gbps). A value of 0 ps will disable
144 the DLL phase shift between 1000 ps (45 degree shift at 1Gbps) and
145 3300 ps (147 degree shift at 1Gbps). A value of 0 ps will disable
187 #address-cells = <1>;
/linux-6.14.4/drivers/net/phy/
Dphy-core.c27 return "1Gbps"; in phy_speed_to_str()
29 return "2.5Gbps"; in phy_speed_to_str()
31 return "5Gbps"; in phy_speed_to_str()
33 return "10Gbps"; in phy_speed_to_str()
35 return "14Gbps"; in phy_speed_to_str()
37 return "20Gbps"; in phy_speed_to_str()
39 return "25Gbps"; in phy_speed_to_str()
41 return "40Gbps"; in phy_speed_to_str()
43 return "50Gbps"; in phy_speed_to_str()
45 return "56Gbps"; in phy_speed_to_str()
[all …]
/linux-6.14.4/tools/testing/selftests/drivers/net/mlxsw/
Dqos_lib.sh5 local rate=$1; shift
6 local min=$1; shift
7 local what=$1; shift
14 return 1
19 local sw_in=$1; shift # Where the traffic ingresses the switch
20 local host_in=$1; shift # Where it ingresses another host
21 local counter=$1; shift # Counter to use for measurement
22 local what=$1; shift
29 # 1Gbps. That wouldn't saturate egress and MC would thus get through,
30 # seemingly winning bandwidth on account of UC. Demand at least 2Gbps
[all …]
Dsch_red_core.sh3 # This test sends a >1Gbps stream of traffic from H1, to the switch, which
4 # forwards it to a 1Gbps port. This 1Gbps stream is then looped back to the
5 # switch and forwarded to the port under test $swp3, which is also 1Gbps.
8 # to the backlog. Any extra packets sent should almost 1:1 go to backlog. That
12 # and maximum size are 1 byte apart, so there is a very clear border under which
20 # the implicit mlxsw configuration, where packet priority is taken 1:1 from the
35 # | >1Gbps |
60 # | | | 1Gbps
80 local pid=$1; shift
87 sleep 1
[all …]
Dqos_mc_aware.sh18 # Multicast traffic is untagged, unicast traffic is tagged with PCP 1. Therefore
32 # | traffic | | | e-qos-map 0:1 |
39 # | >1Gbps | | >1Gbps |
41 # | | $swp1.1 + | | + $swp2.111 | |
43 # | | $swp3.1 + | | + $swp3.111 | |
48 # | | 1Gbps bottleneck |
92 ip link set dev $h2.111 type vlan egress-qos-map 0:1
133 tc qdisc replace dev $swp3 root handle 3: tbf rate 1gbit \
134 burst 128K limit 1G
177 devlink_tc_bind_pool_th_save $swp2 1 ingress
[all …]
/linux-6.14.4/fs/smb/client/
Dcifs_debug.c142 seq_printf(m, "\n\n\t\tChannel: %d DISABLED", i+1); in cifs_dump_channel()
151 i+1, server->conn_id, in cifs_dump_channel()
180 return "1Gbps"; in smb_speed_to_str()
182 return "2.5Gbps"; in smb_speed_to_str()
184 return "5Gbps"; in smb_speed_to_str()
186 return "10Gbps"; in smb_speed_to_str()
188 return "14Gbps"; in smb_speed_to_str()
190 return "20Gbps"; in smb_speed_to_str()
192 return "25Gbps"; in smb_speed_to_str()
194 return "40Gbps"; in smb_speed_to_str()
[all …]
/linux-6.14.4/Documentation/networking/
Ddctcp.rst19 switches is 20 packets (30KB) at 1Gbps, and 65 packets (~100KB) at 10Gbps,
/linux-6.14.4/drivers/net/ethernet/hisilicon/hns3/hns3pf/
Dhclge_main.h26 #define HCLGE_VF_VPORT_START_NUM 1
88 #define HCLGE_RSS_TC_SIZE_0 1
151 #define HCLGE_CORE_RESET_BIT 1
166 #define HCLGE_VECTOR0_RX_CMDQ_INT_B 1
168 #define HCLGE_VECTOR0_IMP_RESET_INT_B 1
178 (pci_resource_len((hdev)->pdev, HCLGE_MEM_BAR) >> 1)
188 #define HCLGE_SUPPORT_10G_BIT BIT(1)
247 HCLGE_MAC_SPEED_1G = 1000, /* 1000 Mbps = 1 Gbps */
248 HCLGE_MAC_SPEED_10G = 10000, /* 10000 Mbps = 10 Gbps */
249 HCLGE_MAC_SPEED_25G = 25000, /* 25000 Mbps = 25 Gbps */
[all …]
/linux-6.14.4/arch/arm64/boot/dts/marvell/
Darmada-8040-puzzle-m801.dts58 v_vddo_h: regulator-1-8v {
82 tx-disable-gpios = <&sfpplus_gpio 1 GPIO_ACTIVE_HIGH>;
100 led-1 {
101 /* SFP+ port 1: Activity */
103 function-enumerator = <1>;
108 /* SFP+ port 2: 10 Gbps indicator */
115 /* SFP+ port 2: 1 Gbps indicator */
122 /* SFP+ port 1: 10 Gbps indicator */
129 /* SFP+ port 1: 1 Gbps indicator */
151 no-1-8-v;
[all …]
/linux-6.14.4/drivers/net/phy/realtek/
Drealtek_main.c41 #define RTL8211F_LEDCR_LINK_100 BIT(1)
49 #define RTL8211F_ALDPS_PLL_OFF BIT(1)
673 * 1: Full Duplex in rtlgen_decode_physr()
705 * 1: Master Mode in rtlgen_decode_physr()
743 ret = __phy_read(phydev, 0x10 + ((regnum & 0xf) >> 1)); in rtlgen_read_mmd()
771 ret = __phy_write(phydev, 0x10 + ((regnum & 0xf) >> 1), val); in rtlgen_write_mmd()
1133 return is_c45 && (id == phydev->c45_ids.device_ids[1]); in rtlgen_is_c45_match()
1234 if (ret == 1) in rtl9000a_config_aneg()
1431 .name = "RTL8226 2.5Gbps PHY",
1442 .name = "RTL8226B_RTL8221B 2.5Gbps PHY",
[all …]
/linux-6.14.4/include/rdma/
Dopa_port_info.h15 #define OPA_PORT_PACKET_FORMAT_8B 1 /* Format 8B */
21 #define OPA_PORT_LTP_CRC_MODE_14 1 /* 14-bit LTP CRC mode (optional) */
28 #define OPA_LINKDOWN_REASON_RCV_ERROR_0 1
89 #define OPA_LINKINIT_REASON_LINKUP (1 << 4)
96 #define OPA_LINK_SPEED_NOP 0x0000 /* Reserved (1-5 Gbps) */
97 #define OPA_LINK_SPEED_12_5G 0x0001 /* 12.5 Gbps */
98 #define OPA_LINK_SPEED_25G 0x0002 /* 25.78125? Gbps (EDR) */
105 #define OPA_CAP_MASK3_IsEthOnFabricSupported (1 << 13)
106 #define OPA_CAP_MASK3_IsSnoopSupported (1 << 7)
107 #define OPA_CAP_MASK3_IsAsyncSC2VLSupported (1 << 6)
[all …]

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