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/linux-6.14.4/arch/arm/mach-socfpga/
Dcore.h10 #define SOCFPGA_RSTMGR_CTRL 0x04
11 #define SOCFPGA_RSTMGR_MODMPURST 0x10
12 #define SOCFPGA_RSTMGR_MODPERRST 0x14
13 #define SOCFPGA_RSTMGR_BRGMODRST 0x1c
15 #define SOCFPGA_A10_RSTMGR_CTRL 0xC
16 #define SOCFPGA_A10_RSTMGR_MODMPURST 0x20
19 #define RSTMGR_CTRL_SWCOLDRSTREQ 0x1 /* Cold Reset */
20 #define RSTMGR_CTRL_SWWARMRSTREQ 0x2 /* Warm Reset */
22 #define RSTMGR_MPUMODRST_CPU1 0x2 /* CPU1 Reset */
40 #define SOCFPGA_SCU_VIRT_BASE 0xfee00000
/linux-6.14.4/drivers/gpu/drm/xe/regs/
Dxe_gtt_defs.h14 #define GUC_GGTT_TOP 0xFEE00000
34 #define XE_PAGE_PRESENT BIT_ULL(0)
/linux-6.14.4/arch/m68k/include/asm/
Dsun3xprom.h18 #define SUN3X_IOMMU 0x60000000
19 #define SUN3X_ENAREG 0x61000000
20 #define SUN3X_INTREG 0x61001400
21 #define SUN3X_DIAGREG 0x61001800
22 #define SUN3X_ZS1 0x62000000
23 #define SUN3X_ZS2 0x62002000
24 #define SUN3X_LANCE 0x65002000
25 #define SUN3X_EEPROM 0x64000000
26 #define SUN3X_IDPROM 0x640007d8
27 #define SUN3X_VIDEO_BASE 0x50400000
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/linux-6.14.4/arch/x86/include/asm/
Dmsi.h52 #define X86_MSI_BASE_ADDRESS_LOW (0xfee00000 >> 20)
60 #define X86_MSI_BASE_ADDRESS_HIGH (0)
Dapicdef.h14 #define IO_APIC_DEFAULT_PHYS_BASE 0xfec00000
15 #define APIC_DEFAULT_PHYS_BASE 0xfee00000
23 #define APIC_DELIVERY_MODE_FIXED 0
30 #define APIC_ID 0x20
32 #define APIC_LVR 0x30
33 #define APIC_LVR_MASK 0xFF00FF
35 #define GET_APIC_VERSION(x) ((x) & 0xFFu)
36 #define GET_APIC_MAXLVT(x) (((x) >> 16) & 0xFFu)
38 # define APIC_INTEGRATED(x) ((x) & 0xF0u)
42 #define APIC_XAPIC(x) ((x) >= 0x14)
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/linux-6.14.4/arch/powerpc/sysdev/
Dgrackle.c18 #define GRACKLE_CFA(b, d, o) (0x80 | ((b) << 8) | ((d) << 16) \
21 #define GRACKLE_PICR1_LOOPSNOOP 0x00000010
27 out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8)); in grackle_set_loop_snoop()
31 out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8)); in grackle_set_loop_snoop()
38 setup_indirect_pci(hose, 0xfec00000, 0xfee00000, 0); in setup_grackle()
/linux-6.14.4/Documentation/devicetree/bindings/interrupt-controller/
Dintel,ce4100-lapic.yaml67 reg = <0xfee00000 0x1000>;
/linux-6.14.4/arch/powerpc/platforms/embedded6xx/
Dlinkstation.c33 return 0; in declare_of_platform_devices()
49 " bus 0\n", dev); in linkstation_add_bridge()
54 hose->first_busno = bus_range ? bus_range[0] : 0; in linkstation_add_bridge()
55 hose->last_busno = bus_range ? bus_range[1] : 0xff; in linkstation_add_bridge()
56 setup_indirect_pci(hose, 0xfec00000, 0xfee00000, 0); in linkstation_add_bridge()
62 return 0; in linkstation_add_bridge()
88 mpic = mpic_alloc(NULL, 0, 0, 4, 0, " EPIC "); in linkstation_init_IRQ()
92 mpic_assign_isu(mpic, 0, mpic->paddr + 0x10200); in linkstation_init_IRQ()
95 mpic_assign_isu(mpic, 1, mpic->paddr + 0x11000); in linkstation_init_IRQ()
98 mpic_assign_isu(mpic, 2, mpic->paddr + 0x11100); in linkstation_init_IRQ()
Dmpc10x.h24 * Processor: 0x80000000 - 0x807fffff -> PCI I/O: 0x00000000 - 0x007fffff
25 * Processor: 0xc0000000 - 0xdfffffff -> PCI MEM: 0x00000000 - 0x1fffffff
26 * PCI MEM: 0x80000000 -> Processor System Memory: 0x00000000
29 * Processor: 0xfe000000 - 0xfebfffff -> PCI I/O: 0x00000000 - 0x00bfffff
30 * Processor: 0x80000000 - 0xbfffffff -> PCI MEM: 0x80000000 - 0xbfffffff
31 * PCI MEM: 0x00000000 -> Processor System Memory: 0x00000000
40 #define MPC10X_BRIDGE_8240 ((0x0003 << 16) | PCI_VENDOR_ID_MOTOROLA)
41 #define MPC10X_BRIDGE_107 ((0x0004 << 16) | PCI_VENDOR_ID_MOTOROLA)
42 #define MPC10X_BRIDGE_8245 ((0x0006 << 16) | PCI_VENDOR_ID_MOTOROLA)
49 #define MPC10X_MAPA_CNFG_ADDR 0x80000cf8
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/linux-6.14.4/Documentation/arch/x86/
Diommu.rst74 Interrupt ranges are not address translated, (0xfee00000 - 0xfeefffff).
105 ACPI: DMAR (v001 A M I OEMDMAR 0x00000001 MSFT 0x00000097) @ 0x000000007f5b5ef0
113 ACPI DMAR:DRHD (flags: 0x00000000)base: 0x00000000fed90000
114 ACPI DMAR:DRHD (flags: 0x00000000)base: 0x00000000fed91000
115 ACPI DMAR:DRHD (flags: 0x00000001)base: 0x00000000fed93000
116 ACPI DMAR:RMRR base: 0x00000000000ed000 end: 0x00000000000effff
117 ACPI DMAR:RMRR base: 0x000000007f600000 end: 0x000000007fffffff
150 AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0007 address=0xffffc02000 flags=0x0000]
151 AMD-Vi: Event logged [IO_PAGE_FAULT device=07:00.0 domain=0x0007 address=0xffffc02000 flags=0x0000]
/linux-6.14.4/arch/powerpc/boot/dts/fsl/
Dge_imp3a.dts22 reg = <0 0xfef05000 0 0x1000>;
24 ranges = <0x0 0x0 0x0 0xff000000 0x01000000
25 0x1 0x0 0x0 0xe0000000 0x08000000
26 0x2 0x0 0x0 0xe8000000 0x08000000
27 0x3 0x0 0x0 0xfc100000 0x00020000
28 0x4 0x0 0x0 0xfc000000 0x00008000
29 0x5 0x0 0x0 0xfc008000 0x00008000
30 0x6 0x0 0x0 0xfee00000 0x00040000
31 0x7 0x0 0x0 0xfee80000 0x00040000>;
33 /* nor@0,0 is a mirror of part of the memory in nor@1,0
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Dc293pcie.dts46 reg = <0xf 0xffe1e000 0 0x2000>;
47 ranges = <0x0 0x0 0xf 0xec000000 0x04000000
48 0x1 0x0 0xf 0xff800000 0x00010000
49 0x2 0x0 0xf 0xffdf0000 0x00010000>;
54 ranges = <0x0 0xf 0xffe00000 0x100000>;
58 reg = <0xf 0xffe0a000 0 0x1000>;
59 ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000
60 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
61 pcie@0 {
62 ranges = <0x2000000 0x0 0x80000000
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/linux-6.14.4/arch/parisc/include/asm/
Dio.h13 return 0; in isa_bus_to_virt()
18 return 0; in isa_virt_to_bus()
27 * eg dev->hpa or 0xfee00000.
36 " rsm %3,%0\n" in gsc_readb()
37 " ldbx 0(%2),%1\n" in gsc_readb()
38 " mtsm %0\n" in gsc_readb()
50 " rsm %3,%0\n" in gsc_readw()
51 " ldhx 0(%2),%1\n" in gsc_readw()
52 " mtsm %0\n" in gsc_readw()
63 " ldwax 0(%1),%0\n" in gsc_readl()
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/linux-6.14.4/arch/x86/kernel/
Djailhouse.c48 if (boot_cpu_data.cpuid_level < 0 || in jailhouse_cpuid_base()
50 return 0; in jailhouse_cpuid_base()
52 return hypervisor_cpuid_base("Jailhouse\0\0\0", 0); in jailhouse_cpuid_base()
62 memset(now, 0, sizeof(*now)); in jailhouse_get_wallclock()
103 register_lapic_address(0xfee00000); in jailhouse_parse_smp_config()
105 for (cpu = 0; cpu < setup_data.v1.num_cpus; cpu++) in jailhouse_parse_smp_config()
111 mp_register_ioapic(0, 0xfec00000, gsi_top, &ioapic_cfg); in jailhouse_parse_smp_config()
137 if (pcibios_last_bus < 0) in jailhouse_pci_arch_init()
138 pcibios_last_bus = 0xff; in jailhouse_pci_arch_init()
142 pci_mmconfig_add(0, 0, pcibios_last_bus, in jailhouse_pci_arch_init()
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/linux-6.14.4/arch/x86/platform/ce4100/
Dfalconfalls.dts16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
26 soc@0 {
36 reg = <0xfec00000 0x1000>;
41 reg = <0xfed00000 0x200>;
46 reg = <0xfee00000 0x1000>;
54 bus-range = <0 0>;
55 ranges = <0x2000000 0 0xbffff000 0xbffff000 0 0x1000
56 0x2000000 0 0xdffe0000 0xdffe0000 0 0x1000
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/linux-6.14.4/drivers/net/ethernet/cirrus/
Dcs89x0.h18 #define PP_ChipID 0x0000 /* offset 0h -> Corp -ID */
22 #define PP_ISAIOB 0x0020 /* IO base address */
23 #define PP_CS8900_ISAINT 0x0022 /* ISA interrupt select */
24 #define PP_CS8920_ISAINT 0x0370 /* ISA interrupt select */
25 #define PP_CS8900_ISADMA 0x0024 /* ISA Rec DMA channel */
26 #define PP_CS8920_ISADMA 0x0374 /* ISA Rec DMA channel */
27 #define PP_ISASOF 0x0026 /* ISA DMA offset */
28 #define PP_DmaFrameCnt 0x0028 /* ISA DMA Frame count */
29 #define PP_DmaByteCnt 0x002A /* ISA DMA Byte count */
30 #define PP_CS8900_ISAMemB 0x002C /* Memory base */
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/linux-6.14.4/arch/sh/boards/
Dboard-sh7757lcr.c27 .start = 0xffec005c, /* PUDR */
28 .end = 0xffec005c,
32 static unsigned char heartbeat_bit_pos[] = { 0, 1, 2, 3 };
51 #define GBECONT 0xffc10100
56 if (((unsigned long)addr & 0x00000fff) < 0x0800) in sh7757_eth_set_mdio_gate()
64 .start = 0xfef00000,
65 .end = 0xfef001ff,
68 .start = evt2irq(0xc80),
69 .end = evt2irq(0xc80),
82 .id = 0,
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/linux-6.14.4/arch/arm/include/asm/
Dio.h70 asm volatile("strh %1, %0" in __raw_writew()
78 asm volatile("ldrh %0, %1" in __raw_readw()
88 asm volatile("strb %1, %0" in __raw_writeb()
95 asm volatile("str %1, %0" in __raw_writel()
103 asm volatile("ldrb %0, %1" in __raw_readb()
113 asm volatile("ldr %0, %1" in __raw_readl()
122 #define MT_DEVICE 0
134 * The _caller variety takes a __builtin_return_address(0) value for
167 #define __iormb() do { } while (0)
168 #define __iowmb() do { } while (0)
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/linux-6.14.4/drivers/gpu/drm/i915/gt/uc/
Dintel_guc.h338 return intel_guc_ct_send(&guc->ct, action, len, NULL, 0, 0); in intel_guc_send()
345 return intel_guc_ct_send(&guc->ct, action, len, NULL, 0, in intel_guc_send_nb()
354 response_buf, response_buf_size, 0); in intel_guc_send_and_receive()
401 #define GUC_GGTT_TOP 0xFEE00000
409 * [0, ggtt.pin_bias), which is reserved for Boot ROM, SRAM and WOPCM.
410 * Currently, in order to exclude [0, ggtt.pin_bias) address space from
493 guc->mmio_msg = 0; in intel_guc_sanitize()
495 return 0; in intel_guc_sanitize()
/linux-6.14.4/arch/m68k/kernel/
Dhead.S308 TC_ENABLE = 0x8000
309 TC_PAGE8K = 0x4000
310 TC_PAGE4K = 0x0000
313 TTR_ENABLE = 0x8000 /* enable transparent translation */
314 TTR_ANYMODE = 0x4000 /* user and kernel mode access */
315 TTR_KERNELMODE = 0x2000 /* only kernel mode access */
316 TTR_USERMODE = 0x0000 /* only user mode access */
317 TTR_CI = 0x0400 /* inhibit cache */
318 TTR_RW = 0x0200 /* read/write mode */
319 TTR_RWM = 0x0100 /* read/write mask */
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/linux-6.14.4/drivers/phy/rockchip/
Dphy-rockchip-naneng-combphy.c3 * Rockchip PIPE USB3.0 PCIE SATA Combo Phy driver
24 #define PHYREG6 0x14
29 #define PHYREG7 0x18
33 #define PHYREG7_RX_RTERM_MASK GENMASK(3, 0)
34 #define PHYREG7_RX_RTERM_SHIFT 0
37 #define PHYREG8 0x1C
40 #define PHYREG10 0x24
41 #define PHYREG10_SSC_PCM_MASK GENMASK(3, 0)
44 #define PHYREG11 0x28
45 #define PHYREG11_SU_TRIM_0_7 0xF0
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/linux-6.14.4/arch/arm64/boot/dts/rockchip/
Drk3399-base.dtsi51 #size-cells = <0>;
79 cpu_l0: cpu@0 {
82 reg = <0x0 0x0>;
89 i-cache-size = <0x8000>;
92 d-cache-size = <0x8000>;
101 reg = <0x0 0x1>;
108 i-cache-size = <0x8000>;
111 d-cache-size = <0x8000>;
120 reg = <0x0 0x2>;
127 i-cache-size = <0x8000>;
[all …]
Drk3588-base.dtsi56 #size-cells = <0>;
91 cpu_l0: cpu@0 {
94 reg = <0x0>;
115 reg = <0x100>;
134 reg = <0x200>;
153 reg = <0x300>;
172 reg = <0x400>;
193 reg = <0x500>;
212 reg = <0x600>;
233 reg = <0x700>;
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/linux-6.14.4/drivers/iommu/amd/
Diommu.c51 #define MSI_RANGE_START (0xfee00000)
52 #define MSI_RANGE_END (0xfeefffff)
53 #define HT_RANGE_START (0xfd00000000ULL)
54 #define HT_RANGE_END (0xffffffffffULL)
127 amd_iommu_atomic128_set(&ptr->data128[0], new->data128[0]); in write_dte_lower128()
150 if (!(ptr->data[0] & DTE_FLAG_V)) { in update_dte256()
155 } else if (!(new->data[0] & DTE_FLAG_V)) { in update_dte256()
160 } else if (!FIELD_GET(DTE_FLAG_GV, ptr->data[0])) { in update_dte256()
168 } else if (!FIELD_GET(DTE_FLAG_GV, new->data[0])) { in update_dte256()
217 dte->data128[0] = ptr->data128[0]; in get_dte256()
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/linux-6.14.4/drivers/iommu/intel/
Diommu.c40 #define IS_AZALIA(pdev) ((pdev)->vendor == 0x8086 && (pdev)->device == 0x3a3e)
42 #define IOAPIC_RANGE_START (0xfee00000)
43 #define IOAPIC_RANGE_END (0xfeefffff)
44 #define IOVA_START_ADDR (0x1000)
64 static int force_on = 0;
77 return 0; in root_entry_lctp()
89 return 0; in root_entry_uctp()
106 return 0; in device_rid_cmp_key()
156 return 0; in device_rbtree_insert()
207 int intel_iommu_enabled = 0;
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