Lines Matching +full:0 +full:xfee00000
308 TC_ENABLE = 0x8000
309 TC_PAGE8K = 0x4000
310 TC_PAGE4K = 0x0000
313 TTR_ENABLE = 0x8000 /* enable transparent translation */
314 TTR_ANYMODE = 0x4000 /* user and kernel mode access */
315 TTR_KERNELMODE = 0x2000 /* only kernel mode access */
316 TTR_USERMODE = 0x0000 /* only user mode access */
317 TTR_CI = 0x0400 /* inhibit cache */
318 TTR_RW = 0x0200 /* read/write mode */
319 TTR_RWM = 0x0100 /* read/write mask */
320 TTR_FCB2 = 0x0040 /* function code base bit 2 */
321 TTR_FCB1 = 0x0020 /* function code base bit 1 */
322 TTR_FCB0 = 0x0010 /* function code base bit 0 */
323 TTR_FCM2 = 0x0004 /* function code mask bit 2 */
324 TTR_FCM1 = 0x0002 /* function code mask bit 1 */
325 TTR_FCM0 = 0x0001 /* function code mask bit 0 */
328 CC6_ENABLE_D = 0x80000000 /* enable data cache (680[46]0) */
329 CC6_FREEZE_D = 0x40000000 /* freeze data cache (68060) */
330 CC6_ENABLE_SB = 0x20000000 /* enable store buffer (68060) */
331 CC6_PUSH_DPI = 0x10000000 /* disable CPUSH invalidation (68060) */
332 CC6_HALF_D = 0x08000000 /* half-cache mode for data cache (68060) */
333 CC6_ENABLE_B = 0x00800000 /* enable branch cache (68060) */
334 CC6_CLRA_B = 0x00400000 /* clear all entries in branch cache (68060) */
335 CC6_CLRU_B = 0x00200000 /* clear user entries in branch cache (68060) */
336 CC6_ENABLE_I = 0x00008000 /* enable instruction cache (680[46]0) */
337 CC6_FREEZE_I = 0x00004000 /* freeze instruction cache (68060) */
338 CC6_HALF_I = 0x00002000 /* half-cache mode for instruction cache (68060) */
339 CC3_ALLOC_WRITE = 0x00002000 /* write allocate mode(68030) */
340 CC3_ENABLE_DB = 0x00001000 /* enable data burst (68030) */
341 CC3_CLR_D = 0x00000800 /* clear data cache (68030) */
342 CC3_CLRE_D = 0x00000400 /* clear entry in data cache (68030) */
343 CC3_FREEZE_D = 0x00000200 /* freeze data cache (68030) */
344 CC3_ENABLE_D = 0x00000100 /* enable data cache (68030) */
345 CC3_ENABLE_IB = 0x00000010 /* enable instruction burst (68030) */
346 CC3_CLR_I = 0x00000008 /* clear instruction cache (68030) */
347 CC3_CLRE_I = 0x00000004 /* clear entry in instruction cache (68030) */
348 CC3_FREEZE_I = 0x00000002 /* freeze instruction cache (68030) */
349 CC3_ENABLE_I = 0x00000001 /* enable instruction cache (68030) */
404 .macro func_start name,saveregs,stack=0
432 .macro func_define name,nr=0
580 .long 0
615 leds 0x1
755 movew #0x2700,%sr
764 phys. 0x0. This should result in a bus error on all other machines.
767 same behaviour (0x0..0x7 are no ROM shadow). So we have to do
769 read attempt for 0x00ff82fe phys. that should bus error on a Falcon
772 The test for the Hades is done by reading address 0xb0000000. This
780 moveq #0,%d3 /* default if tag doesn't exist */
789 * serial port. There are no I/O regs at 0x00ffxxxx at all. */
790 moveq #0,%d0
793 movel #0xff000000,%d0 /* Hades I/O base addr: 0xff000000 */
832 .word 0x70 /* trap 0x70 - .BRD_ID */
893 leds 0x2
910 leds 0x4
951 * 040: Map the 16Meg range physical 0x0 up to logical 0x8000.0000
953 mmu_map #0x80000000,#0,#0x01000000,#_PAGE_NOCACHE_S
958 mmu_map_tt #1,#0x40000000,#0x20000000,#_PAGE_NOCACHE_S
964 * 030: Map the 32Meg range physical 0x0 up to logical 0x8000.0000
966 mmu_map #0x80000000,#0,#0x02000000,#_PAGE_NOCACHE030
967 mmu_map_tt #1,#0x40000000,#0x20000000,#_PAGE_NOCACHE030
982 /* On the Atari, we map the I/O region (phys. 0x00ffxxxx) by mapping
984 0xffxxxxxx -> 0x00xxxxxx). For this, an additional pointer table is
988 (i.e. 0xffxxxxxx -> 0xffxxxxxx), because some I/O registers are
995 /* I/O base addr for non-Medusa, non-Hades: 0x00000000 */
996 moveq #0,%d0
1002 2: movel #0xff000000,%d0 /* Medusa/Hades base addr: 0xff000000 */
1008 * need to disable caches (crucial only for 0xff8000..0xffffff
1009 * (standard I/O) and 0xf00000..0xf3ffff (IDE)). The remainder
1011 * ROMs (mirror at phys. 0x0), so caching isn't necessary for
1013 mmu_map #0xff000000,%d3,#0x01000000,#_PAGE_NOCACHE030
1019 mmu_map #0xff000000,%d3,#0x01000000,#_PAGE_NOCACHE_S
1029 * add transparent mapping for 0xff00 0000 - 0xffff ffff
1032 * 0xfe000000-0xfeffffff is for screen and ROM
1037 mmu_map_tt #0,#0xfe000000,#0x01000000,#_PAGE_CACHE040W
1038 mmu_map_tt #1,#0xff000000,#0x01000000,#_PAGE_NOCACHE_S
1048 /* On the HP300, we map the ROM, INTIO and DIO regions (phys. 0x00xxxxxx)
1049 * by mapping 32MB (on 020/030) or 16 MB (on 040) from 0xf0xxxxxx -> 0x00xxxxxx).
1056 * 030: Map the 32Meg range physical 0x0 up to logical 0xf000.0000
1058 mmu_map #0xf0000000,#0,#0x02000000,#_PAGE_NOCACHE030
1064 * 040: Map the 16Meg range physical 0x0 up to logical 0xf000.0000
1066 mmu_map #0xf0000000,#0,#0x01000000,#_PAGE_NOCACHE_S
1079 * 4MB of RAM at address 0, so now need to do a transparent
1084 mmu_map_tt #1,#0xe0000000,#0x20000000,#_PAGE_NOCACHE030
1097 * 4MB of RAM at address 0, so now need to do a transparent
1103 * IO is in the range 0xfff00000 to 0xfffeffff.
1104 * PROM is 0xff800000->0xffbfffff and SRAM is
1105 * 0xffe00000->0xffe1ffff.
1108 mmu_map_tt #1,#0xe0000000,#0x20000000,#_PAGE_NOCACHE_S
1121 * 4MB of RAM at address 0, so now need to do a transparent
1128 mmu_map_tt #1,#0xe0000000,#0x20000000,#_PAGE_NOCACHE_S
1147 * 0x5000.0000 ... 0x5300.0000 range,
1151 * 0x0000.0000 then we know there is valid RAM just
1154 * By the way, if the frame buffer is at 0x0000.0000
1179 * Mac Note: screen address of logical 0xF000.0000 -> <screen physical>
1188 mmu_map_eq #0x40000000,#0x02000000,%d3
1190 mmu_map_eq #0x50000000,#0x03000000,%d3
1191 /* Nubus slot space (video at 0xF0000000, rom at 0xF0F80000) */
1192 mmu_map_tt #1,#0xf8000000,#0x08000000,%d3
1207 /* copy maps from 0xfee00000 to 0xff000000 */
1208 movel #0xfee00000, %d0
1213 movel #0xfee00000, %d0
1219 movel #0xfee00000, %d0
1226 movel 0xfefe00d4, %a1
1229 movel #((0x200000 >> 13)-1), %d1
1234 addl #0x1000,%d3
1240 mmu_map_tt #1,#0x40000000,#0x40000000,#_PAGE_NOCACHE_S
1248 mmu_map_tt #1,#0xFF000000,#0x01000000,#_PAGE_NOCACHE_S
1257 mmu_map #0x80000000,#0,#0x02000000,#_PAGE_NOCACHE030
1266 leds 0x8
1340 * the logical memory for the kernel, i.e., 0x01000.
1341 * B. The kernel is located some where else. e.g., 0x0400.0000
1352 * then create a mapping for the kernel at logical 0x8000.0000 to
1355 * is engaged, the PC can be moved up into the 0x8000.0000 range
1361 * is made in page 0 (an as of yet unused location -- except for the
1369 * Last, if _start is already at 0x01000, then there's nothing special
1400 movel #0xff000000,L(iobase)
1416 orl #0x50000000,L(mac_sccbase)
1425 movel #0xf0000000,L(iobase)
1431 movel #0x60,0xf05f400c
1437 1: movew #0,0xf05f400e
1438 movew #0x64,0xf05f400e
1446 oriw #0x4000,0x61000000
1456 movel #0x80000000,L(iobase)
1461 leds 0x10
1522 leds 0x55
1542 2: moveq #0,%d0
1598 * bits 11..0 - offset into a particular 4K page
1625 #define mmu_next_valid 0
1633 #define MMU_PRINT_UNINITED 0
1650 #if 0
1658 #if 0
1670 andil #0xFFFFFE00,%d7
1682 andil #0xFFFFFF00,%d7
1690 btst #0,%d6
1717 movel #0x00000000,%a4 /* logical address */
1718 moveql #0,%d0
1729 movel #0,%d1
1730 andil #0xfffffe00,%d6
1741 movel #0,%d2
1742 andil #0xffffff00,%d6
1748 btst #0,%d6
1756 andil #0xfffff4e0,%d1
1779 andiw #0x8000,%d1 /* is it valid ? */
1783 andil #0xff000000,%d1 /* Get the address */
1793 andiw #0x8000,%d1 /* is it valid ? */
1797 andil #0xff000000,%d1 /* Get the address */
1839 andil #0xfffffff0,%d0
1841 movel #0x00000000,%a4 /* logical address */
1842 movel #0,%d0
1849 btst #0,%d6 /* is it early terminating? */
1857 movel #0,%d1
1858 andil #0xfffffff0,%d6
1866 btst #0,%d6 /* is it a page descriptor? */
1874 movel #0,%d2
1875 andil #0xfffffff0,%d6
1881 btst #0,%d6
1986 puts "cputype: 0"
1995 9: putc '0'
2023 bfffo ARG3{#0,#32},%d1
2400 alignment restriction for pointer tables on the '0[46]0. */
2498 movel #0x80000002,%a0@
2500 movel #0x0808,%d0
2508 movel #0x82c07760,%a0@(8)
2512 movel #0x0808,%d0
2530 #if 0
2587 #if 0
2598 #if 0
2648 #if 0
2658 #if 0
2702 #if 0
2753 .byte 4,0x44 /* x16, 1 stopbit, no parity */
2754 .byte 3,0xc0 /* receiver: 8 bpc */
2755 .byte 5,0xe2 /* transmitter: 8 bpc, assert dtr/rts */
2756 .byte 10,0 /* NRZ */
2757 .byte 11,0x50 /* use baud rate generator */
2758 .byte 12,1,13,0 /* 38400 baud */
2760 .byte 3,0xc1 /* enable receiver */
2761 .byte 5,0xea /* enable transmitter */
2777 .byte 4,0x44 /* x16, 1 stopbit, no parity */
2778 .byte 3,0xc0 /* receiver: 8 bpc */
2779 .byte 5,0xe2 /* transmitter: 8 bpc, assert dtr/rts */
2780 .byte 10,0 /* NRZ */
2781 .byte 11,0x50 /* use baud rate generator */
2782 .byte 12,24,13,0 /* 9600 baud */
2784 .byte 3,0xc1 /* enable receiver */
2785 .byte 5,0xea /* enable transmitter */
2792 LPSG_SELECT = 0xff8800
2793 LPSG_READ = 0xff8800
2794 LPSG_WRITE = 0xff8802
2798 LSTMFP_GPIP = 0xfffa01
2799 LSTMFP_DDR = 0xfffa05
2800 LSTMFP_IERB = 0xfffa09
2804 LSCC_CTRL = 0xff8c85
2805 LSCC_DATA = 0xff8c87
2809 LSCC_CTRL = 0xff8c81
2810 LSCC_DATA = 0xff8c83
2814 LMFP_UCR = 0xfffa29
2815 LMFP_TDCDR = 0xfffa1d
2816 LMFP_TDDR = 0xfffa25
2817 LMFP_TSR = 0xfffa2d
2818 LMFP_UDR = 0xfffa2f
2864 bclr #0,%a1@(LSTMFP_IERB)
2865 bclr #0,%a1@(LSTMFP_DDR)
2867 moveb #0xff,%a1@(LPSG_WRITE)
2880 moveb #0xc0,%a0@
2897 moveb #0x88,%a1@(LMFP_UCR)
2898 andb #0x70,%a1@(LMFP_TDCDR)
2910 #define mac_scc_cha_b_ctrl_offset 0x0
2911 #define mac_scc_cha_a_ctrl_offset 0x2
2912 #define mac_scc_cha_b_data_offset 0x4
2913 #define mac_scc_cha_a_data_offset 0x6
2919 moveb #0xc0,%a0@(mac_scc_cha_a_ctrl_offset)
2956 move.l #0xff020010,%a1@ /* must be inited - also used by debug=mem */
2957 move.l #0xff020000,%a1
2972 /*nodbg: q40_do_debug is 0 by default*/
2978 moveb #0x10,M167_PCSCCMICR
2979 moveb #0x10,M167_PCSCCTICR
2980 moveb #0x10,M167_PCSCCRICR
3011 andw #0x00ff,%d0
3012 oriw #0x0100,%d0
3016 andw #0x2000,%d0
3045 3: btst #0,%a1@(LSTMFP_GPIP)
3109 moveb #0,M167_CYCAR
3111 moveb #0x02,M167_CYIER
3118 moveb #0x08,M167_CYTEOIR
3122 moveb #0,M167_CYTEOIR
3128 .word 0x0020 /* TRAP 0x020 */
3150 movel 0xFEFE0018,%a1
3175 andb #0x4,%d0
3190 andb #0x20,%d1
3195 andb #0x20,%d1
3244 andb #0x0f,%d2
3245 addb #'0',%d2
3275 ori #0x0700,%sr
3302 moveb %d0,%a0@(0x1ffff)
3309 eorw #0xff00,%d0
3321 #define Lconsole_struct_cur_column 0
3348 andl #0xffff,%d3 /* d3 = screen width in pixels */
3349 andl #0xffff,%d4 /* d4 = screen height in pixels */
3374 lea 0,%a0
3428 andil #0xffff,%d0
3481 andl #0xffff,%d3 /* d3 = screen width in pixels */
3482 andl #0xffff,%d4 /* d4 = screen height in pixels */
3598 andl #0x000000ff,%d7
3607 * d2 = (bit 0) 1/0 for white/black (!) pixel on screen
3643 * d2 = (bit 0) 1/0 for white/black (!)
3659 * d2 = black or white (0/1)
3739 moveb #0xff,%a1@
3756 movew #0x0fff,%a1@
3768 .long 0
3774 .long 0
3779 .long 0 /* cursor column */
3780 .long 0 /* cursor row */
3781 .long 0 /* max num columns */
3782 .long 0 /* max num rows */
3783 .long 0 /* left edge */
3785 .long 0 /* pointer to console font (struct font_desc) */
3787 .long 0 /* pointer to console font data */
3792 .long 0 /* valid flag */
3793 .long 0 /* start logical */
3794 .long 0 /* next logical */
3795 .long 0 /* start physical */
3796 .long 0 /* next physical */
3800 .long 0
3802 .long 0
3804 .long 0
3806 .long 0
3808 .long 0
3810 .long 0
3812 .long 0
3814 .long 0
3817 M147_SCC_CTRL_A = 0xfffe3002
3818 M147_SCC_DATA_A = 0xfffe3003
3822 M162_SCC_CTRL_A = 0xfff45005
3823 M167_CYCAR = 0xfff450ee
3824 M167_CYIER = 0xfff45011
3825 M167_CYLICR = 0xfff45026
3826 M167_CYTEOIR = 0xfff45085
3827 M167_CYTDR = 0xfff450f8
3828 M167_PCSCCMICR = 0xfff4201d
3829 M167_PCSCCTICR = 0xfff4201e
3830 M167_PCSCCRICR = 0xfff4201f
3831 M167_PCTPIACKR = 0xfff42025
3835 BVME_SCC_CTRL_A = 0xffb0000b
3836 BVME_SCC_DATA_A = 0xffb0000f
3841 .long 0
3843 .long 0
3845 .long 0
3847 .long 0
3849 .long 0
3853 LSRB0 = 0x10412
3854 LTHRB0 = 0x10416
3855 LCPUCTRL = 0x10100
3859 DCADATA = 0x11
3860 DCALSR = 0x1b
3861 APCIDATA = 0x00
3862 APCILSR = 0x14
3864 .long 0
3874 .long 0
3876 .long 0
3878 .long 0
3881 .long 0,0,0,0,0,0,0,0
3885 .long 0
3887 .long 0
3891 GF_PUT_CHAR = 0x00
3893 .long 0