Searched +full:0 +full:xe6180000 (Results 1 – 25 of 32) sorted by relevance
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19 #define CPG_BASE2 0xe615100020 #define WUPCR 0x10 /* System-CPU Wake Up Control Register */21 #define SRESCR 0x18 /* System-CPU Software Reset Control Register */22 #define PSTR 0x40 /* System-CPU Power Status Register */24 #define SYSC_BASE 0xe618000025 #define SBAR 0x20 /* SYS Boot Address Register */27 #define AP_BASE 0xe6f1000028 #define APARMBAREA 0x20 /* Address Translation Area Register */30 #define SH73A0_SCU_BASE 0xf000000042 return 0; in sh73a0_boot_secondary()[all …]
28 - renesas,r8a774a3-sysc # RZ/G2M v3.069 reg = <0xe6180000 0x0200>;
45 const: 077 const: 080 const: 095 reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;100 #size-cells = <0>;101 #power-domain-cells = <0>;106 #size-cells = <0>;107 #power-domain-cells = <0>;111 #power-domain-cells = <0>;117 #power-domain-cells = <0>;
20 #size-cells = <0>;21 cpu@0 {24 reg = <0x0>;35 reg = <0xc2800000 0x1000>,36 <0xc2000000 0x1000>;41 reg = <0xf0100000 0x1000>;53 reg = <0xfe400000 0x400>;68 reg = <0xfe910000 0x3000>;77 reg = <0xfe914000 0x3000>;87 reg = <0xe6138000 0x170>;[all …]
21 #size-cells = <0>;23 cpu0: cpu@0 {26 reg = <0>;33 L2_CA15: cache-controller-0 {66 reg = <0 0xe61e0000 0 0x30>;79 reg = <0 0xfff80000 0 0x30>;92 reg = <0 0xe6790000 0 0x10000>;98 reg = <0 0xe67a0000 0 0x10000>;104 #size-cells = <0>;106 reg = <0 0xe60b0000 0 0x428>;[all …]
40 #clock-cells = <0>;42 clock-frequency = <0>;47 #size-cells = <0>;49 cpu0: cpu@0 {52 reg = <0>;71 L2_CA15: cache-controller-0 {82 #clock-cells = <0>;84 clock-frequency = <0>;91 ranges = <0 0 0 0x1c000000>;104 #clock-cells = <0>;[all …]
20 #size-cells = <0>;22 cpu0: cpu@0 {25 reg = <0>;44 reg = <0xf0000200 0x100>;51 reg = <0xf0000600 0x20>;60 reg = <0xf0001000 0x1000>,61 <0xf0000100 0x100>;66 reg = <0xf0100000 0x1000>;78 reg = <0xfb400000 0x400>;87 reg = <0xfe400000 0x400>;[all …]
27 #size-cells = <0>;29 cpu0: cpu@0 {32 reg = <0>;51 L2_CA7: cache-controller-0 {62 #clock-cells = <0>;64 clock-frequency = <0>;77 #clock-cells = <0>;79 clock-frequency = <0>;93 reg = <0 0xe6020000 0 0x0c>;104 reg = <0 0xe6050000 0 0x50>;[all …]
34 * The external audio clocks are configured as 0 Hz fixed frequency40 #clock-cells = <0>;41 clock-frequency = <0>;45 #clock-cells = <0>;46 clock-frequency = <0>;50 #clock-cells = <0>;51 clock-frequency = <0>;57 #clock-cells = <0>;59 clock-frequency = <0>;64 #size-cells = <0>;[all …]
32 * The external audio clocks are configured as 0 Hz fixed frequency38 #clock-cells = <0>;39 clock-frequency = <0>;43 #clock-cells = <0>;44 clock-frequency = <0>;48 #clock-cells = <0>;49 clock-frequency = <0>;55 #clock-cells = <0>;57 clock-frequency = <0>;62 #size-cells = <0>;[all …]
36 * The external audio clocks are configured as 0 Hz fixed42 #clock-cells = <0>;43 clock-frequency = <0>;47 #clock-cells = <0>;48 clock-frequency = <0>;52 #clock-cells = <0>;53 clock-frequency = <0>;59 #clock-cells = <0>;61 clock-frequency = <0>;66 #size-cells = <0>;[all …]
19 * The external audio clocks are configured as 0 Hz fixed frequency25 #clock-cells = <0>;26 clock-frequency = <0>;31 #clock-cells = <0>;32 clock-frequency = <0>;37 #clock-cells = <0>;38 clock-frequency = <0>;44 #clock-cells = <0>;46 clock-frequency = <0>;51 #size-cells = <0>;[all …]
41 * The external audio clocks are configured as 0 Hz fixed frequency47 #clock-cells = <0>;48 clock-frequency = <0>;52 #clock-cells = <0>;53 clock-frequency = <0>;57 #clock-cells = <0>;58 clock-frequency = <0>;64 #clock-cells = <0>;66 clock-frequency = <0>;71 #size-cells = <0>;[all …]
19 * The external audio clocks are configured as 0 Hz fixed frequency25 #clock-cells = <0>;26 clock-frequency = <0>;30 #clock-cells = <0>;31 clock-frequency = <0>;35 #clock-cells = <0>;36 clock-frequency = <0>;42 #clock-cells = <0>;44 clock-frequency = <0>;49 #size-cells = <0>;[all …]
40 * The external audio clocks are configured as 0 Hz fixed frequency46 #clock-cells = <0>;47 clock-frequency = <0>;51 #clock-cells = <0>;52 clock-frequency = <0>;56 #clock-cells = <0>;57 clock-frequency = <0>;63 #clock-cells = <0>;65 clock-frequency = <0>;70 #size-cells = <0>;[all …]
22 #clock-cells = <0>;23 clock-frequency = <0>;28 #size-cells = <0>;30 a53_0: cpu@0 {33 reg = <0>;60 #clock-cells = <0>;62 clock-frequency = <0>;67 #clock-cells = <0>;69 clock-frequency = <0>;87 #clock-cells = <0>;[all …]
17 cluster01_opp: opp-table-0 {73 #size-cells = <0>;113 a55_0: cpu@0 {115 reg = <0>;127 reg = <0x100>;139 reg = <0x10000>;151 reg = <0x10100>;163 reg = <0x20000>;175 reg = <0x20100>;187 reg = <0x30000>;[all …]
22 #clock-cells = <0>;23 clock-frequency = <0>;28 #size-cells = <0>;30 a53_0: cpu@0 {33 reg = <0>;80 #clock-cells = <0>;82 clock-frequency = <0>;87 #clock-cells = <0>;89 clock-frequency = <0>;95 #clock-cells = <0>;[all …]
19 * The external audio clocks are configured as 0 Hz fixed frequency25 #clock-cells = <0>;26 clock-frequency = <0>;31 #clock-cells = <0>;32 clock-frequency = <0>;38 #clock-cells = <0>;39 clock-frequency = <0>;44 #size-cells = <0>;46 a53_0: cpu@0 {48 reg = <0x0>;[all …]
20 #clock-cells = <0>;21 clock-frequency = <0>;27 #clock-cells = <0>;28 clock-frequency = <0>;31 cluster0_opp: opp-table-0 {48 #size-cells = <0>;67 a76_0: cpu@0 {69 reg = <0>;81 reg = <0x100>;93 reg = <0x200>;[all …]
18 * The external audio clocks are configured as 0 Hz fixed frequency24 #clock-cells = <0>;25 clock-frequency = <0>;30 #clock-cells = <0>;31 clock-frequency = <0>;36 #clock-cells = <0>;37 clock-frequency = <0>;43 #clock-cells = <0>;44 clock-frequency = <0>;71 #size-cells = <0>;[all …]
20 #clock-cells = <0>;21 clock-frequency = <0>;27 #clock-cells = <0>;28 clock-frequency = <0>;31 cluster0_opp: opp-table-0 {66 #size-cells = <0>;88 a76_0: cpu@0 {90 reg = <0>;102 reg = <0x100>;114 reg = <0x10000>;[all …]
20 #clock-cells = <0>;21 clock-frequency = <0>;26 #size-cells = <0>;28 a76_0: cpu@0 {30 reg = <0>;37 L3_CA76_0: cache-controller-0 {47 #clock-cells = <0>;49 clock-frequency = <0>;54 #clock-cells = <0>;56 clock-frequency = <0>;[all …]