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/linux-6.14.4/Documentation/devicetree/bindings/net/wireless/
Dqcom,ath10k.yaml115 enum: [0, 1]
282 reg = <0x18800000 0x800000>;
299 iommus = <&anoc2_smmu 0x1900>,
300 <&anoc2_smmu 0x1901>;
309 iommus = <&apps_smmu 0x1c02 0x1>;
319 reg = <0xa000000 0x200000>;
/linux-6.14.4/sound/soc/fsl/
Dfsl_xcvr.h11 #define FSL_XCVR_MODE_SPDIF 0
16 #define FSL_XCVR_REG_OFFSET 0x800 /* regs offset */
17 #define FSL_XCVR_FIFO_SIZE 0x80 /* 128 */
23 #define FSL_XCVR_RX_FIFO_ADDR 0x0C00
24 #define FSL_XCVR_TX_FIFO_ADDR 0x0E00
26 #define FSL_XCVR_VERSION 0x00 /* Version */
27 #define FSL_XCVR_EXT_CTRL 0x10 /* Control */
28 #define FSL_XCVR_EXT_STATUS 0x20 /* Status */
29 #define FSL_XCVR_EXT_IER0 0x30 /* Interrupt en 0 */
30 #define FSL_XCVR_EXT_IER1 0x40 /* Interrupt en 1 */
[all …]
/linux-6.14.4/arch/arm/boot/dts/hisilicon/
Dhip04.dtsi22 boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>;
27 #size-cells = <0>;
87 CPU0: cpu@0 {
90 reg = <0>;
110 reg = <0x100>;
115 reg = <0x101>;
120 reg = <0x102>;
125 reg = <0x103>;
130 reg = <0x200>;
135 reg = <0x201>;
[all …]
/linux-6.14.4/drivers/accel/habanalabs/goya/
Dgoya_coresight.c18 #define SPMU_EVENT_TYPES_OFFSET 0x400
220 "Timeout while waiting for coresight, addr: 0x%llx, position: %d, up: %d\n", in goya_coresight_timeout()
225 return 0; in goya_coresight_timeout()
243 WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK); in goya_config_stm()
251 WREG32(base_reg + 0xE80, 0x80004); in goya_config_stm()
252 WREG32(base_reg + 0xD64, 7); in goya_config_stm()
253 WREG32(base_reg + 0xD60, 0); in goya_config_stm()
254 WREG32(base_reg + 0xD00, lower_32_bits(input->he_mask)); in goya_config_stm()
255 WREG32(base_reg + 0xD20, lower_32_bits(input->sp_mask)); in goya_config_stm()
256 WREG32(base_reg + 0xD60, 1); in goya_config_stm()
[all …]
/linux-6.14.4/arch/arm/boot/dts/qcom/
Dqcom-ipq4019.dtsi21 #address-cells = <0x1>;
22 #size-cells = <0x1>;
26 reg = <0x87e00000 0x080000>;
31 reg = <0x87e80000 0x180000>;
45 #size-cells = <0>;
46 cpu@0 {
53 reg = <0x0>;
55 clock-frequency = <0>;
67 reg = <0x1>;
69 clock-frequency = <0>;
[all …]
/linux-6.14.4/drivers/media/dvb-frontends/
Dmxl692.c36 int ret = 0; in mxl692_i2c_write()
39 .flags = 0, in mxl692_i2c_write()
53 int ret = 0; in mxl692_i2c_read()
72 for (i = 0; i < (size & ~3); i += 4) { in convert_endian()
73 d[i + 0] ^= d[i + 3]; in convert_endian()
74 d[i + 3] ^= d[i + 0]; in convert_endian()
75 d[i + 0] ^= d[i + 3]; in convert_endian()
83 case 0: in convert_endian()
88 d[i + 0] ^= d[i + 1]; in convert_endian()
89 d[i + 1] ^= d[i + 0]; in convert_endian()
[all …]
/linux-6.14.4/drivers/gpu/drm/amd/include/asic_reg/bif/
Dbif_5_1_d.h27 #define mmMM_INDEX 0x0
28 #define mmMM_INDEX_HI 0x6
29 #define mmMM_DATA 0x1
30 #define mmBIF_MM_INDACCESS_CNTL 0x1500
31 #define mmBUS_CNTL 0x1508
32 #define mmCONFIG_CNTL 0x1509
33 #define mmCONFIG_MEMSIZE 0x150a
34 #define mmCONFIG_F0_BASE 0x150b
35 #define mmCONFIG_APER_SIZE 0x150c
36 #define mmCONFIG_REG_APER_SIZE 0x150d
[all …]
/linux-6.14.4/arch/arm64/boot/dts/qcom/
Dqcs404.dtsi24 #clock-cells = <0>;
30 #clock-cells = <0>;
37 #size-cells = <0>;
42 reg = <0x100>;
56 reg = <0x101>;
70 reg = <0x102>;
84 reg = <0x103>;
104 cpu_sleep_0: cpu-sleep-0 {
107 arm,psci-suspend-param = <0x40000003>;
161 reg = <0 0x80000000 0 0>;
[all …]
/linux-6.14.4/arch/arm64/boot/dts/ti/
Dk3-j784s4-j742s2-main-common.dtsi16 #clock-cells = <0>;
30 reg = <0x00 0x70000000 0x00 0x800000>;
33 ranges = <0x00 0x00 0x70000000 0x800000>;
35 atf-sram@0 {
36 reg = <0x00 0x20000>;
40 reg = <0x1f0000 0x10000>;
44 reg = <0x200000 0x200000>;
50 reg = <0x00 0x00100000 0x00 0x1c000>;
53 ranges = <0x00 0x00 0x00100000 0x1c000>;
57 reg = <0x4034 0x4>;
[all …]