Searched +full:0 +full:x92400000 (Results 1 – 7 of 7) sorted by relevance
176 reg = <0x596e8000 0x88000>;184 mboxes = <&lsio_mu13 2 0>, <&lsio_mu13 2 1>, <&lsio_mu13 3 0>, <&lsio_mu13 3 1>;190 reg = <0x92400000 0x1000000>;194 reg = <0x942f0000 0x8000>;198 reg = <0x942f8000 0x8000>;203 reg = <0x94300000 0x100000>;209 reg = <0x3b6e8000 0x88000>;218 mboxes = <&mu2 0 0>,219 <&mu2 1 0>,220 <&mu2 3 0>;
41 #size-cells = <0>;44 A35_0: cpu@0 {47 reg = <0x0 0x0>;58 reg = <0x0 0x1>;93 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */94 <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */106 reg = <0 0x92400000 0 0x2000000>;126 mboxes = <&lsio_mu1 0 0127 &lsio_mu1 1 0156 reg = <0x2c4 6>;[all …]
59 #size-cells = <0>;62 A35_0: cpu@0 {65 reg = <0x0 0x0>;67 i-cache-size = <0x8000>;70 d-cache-size = <0x8000>;82 reg = <0x0 0x1>;84 i-cache-size = <0x8000>;87 d-cache-size = <0x8000>;99 reg = <0x0 0x2>;101 i-cache-size = <0x8000>;[all …]
32 reg = <0x00000000 0x80000000 0 0x40000000>;41 reg = <0 0x90000000 0 0x8000>;46 reg = <0 0x90008000 0 0x8000>;51 reg = <0 0x90010000 0 0x8000>;56 reg = <0 0x90018000 0 0x8000>;61 reg = <0 0x900ff000 0 0x1000>;66 reg = <0 0x90100000 0 0x8000>;71 reg = <0 0x90108000 0 0x8000>;76 reg = <0 0x90110000 0 0x8000>;81 reg = <0 0x90118000 0 0x8000>;[all …]
17 pinctrl-0 = <&pinctrl_gpio_bkl_on>;18 brightness-levels = <0 45 63 88 119 158 203 255>;28 pinctrl-0 = <&pinctrl_gpio8>;30 gpio-fan,speed-map = < 0 082 pinctrl-0 = <&pinctrl_wifi_pdn>;93 pinctrl-0 = <&pinctrl_gpio7>;105 pinctrl-0 = <&pinctrl_usbh_en>;142 reg = <0 0x84000000 0 0x2000000>;147 reg = <0 0x86000000 0 0x200000>;152 reg = <0 0x86200000 0 0x200000>;[all …]
48 #size-cells = <0>;55 arm,psci-suspend-param = <0x0010033>;64 A53_0: cpu@0 {67 reg = <0x0>;71 i-cache-size = <0x8000>;74 d-cache-size = <0x8000>;88 reg = <0x1>;92 i-cache-size = <0x8000>;95 d-cache-size = <0x8000>;107 reg = <0x2>;[all …]
17 #clock-cells = <0>;21 pinctrl-0 = <&divclk1_default>;26 #clock-cells = <0>;31 pinctrl-0 = <&divclk4_pin_a>;59 pinctrl-0 = <&irled_default>;64 reg = <0x0 0x88800000 0x0 0x1400000>;68 /* This platform has all PIL regions offset by 0x1400000 */71 reg = <0x0 0x89c00000 0x0 0x6200000>;77 reg = <0x0 0x8fe00000 0x0 0x1b00000>;83 reg = <0x0 0x91900000 0x0 0xa00000>;[all …]