Lines Matching +full:0 +full:x92400000
59 #size-cells = <0>;
62 A35_0: cpu@0 {
65 reg = <0x0 0x0>;
67 i-cache-size = <0x8000>;
70 d-cache-size = <0x8000>;
82 reg = <0x0 0x1>;
84 i-cache-size = <0x8000>;
87 d-cache-size = <0x8000>;
99 reg = <0x0 0x2>;
101 i-cache-size = <0x8000>;
104 d-cache-size = <0x8000>;
116 reg = <0x0 0x3>;
118 i-cache-size = <0x8000>;
121 d-cache-size = <0x8000>;
134 cache-size = <0x80000>;
160 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
161 <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
173 reg = <0 0x84000000 0 0x2000000>;
178 reg = <0 0x86000000 0 0x200000>;
183 reg = <0 0x92000000 0 0x100000>;
188 reg = <0 0x92400000 0 0x2000000>;
194 reg = <0 0x94400000 0 0x700000>;
214 mboxes = <&lsio_mu1 0 0
215 &lsio_mu1 1 0
269 #clock-cells = <0>;
270 clock-frequency = <0>;
276 #clock-cells = <0>;
283 #clock-cells = <0>;