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/linux-6.14.4/sound/soc/qcom/
Dlpass-apq8016.c127 int chan = 0; in apq8016_lpass_alloc_dma_channel()
154 return 0; in apq8016_lpass_free_dma_channel()
171 for (i = 0; i < drvdata->num_clks; i++) in apq8016_lpass_init()
208 return 0; in apq8016_lpass_init()
222 return 0; in apq8016_lpass_exit()
227 .i2sctrl_reg_base = 0x1000,
228 .i2sctrl_reg_stride = 0x1000,
230 .irq_reg_base = 0x6000,
231 .irq_reg_stride = 0x1000,
233 .rdma_reg_base = 0x8400,
[all …]
/linux-6.14.4/arch/arm64/boot/dts/qcom/
Dpmk8350.dtsi13 #define PMK8350_SID 0
21 mode-recovery = <0x01>;
22 mode-bootloader = <0x02>;
31 #size-cells = <0>;
35 reg = <0x1300>, <0x800>;
40 interrupts = <PMK8350_SID 0x13 0x7 IRQ_TYPE_EDGE_BOTH>;
47 interrupts = <PMK8350_SID 0x13 0x6 IRQ_TYPE_EDGE_BOTH>;
54 reg = <0x3100>;
56 #size-cells = <0>;
57 interrupts = <PMK8350_SID 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
[all …]
/linux-6.14.4/arch/arm/mach-omap2/
Dprcm43xx.h15 #define AM43XX_PRM_OCP_SOCKET_INST 0x0000
16 #define AM43XX_PRM_MPU_INST 0x0300
17 #define AM43XX_PRM_GFX_INST 0x0400
18 #define AM43XX_PRM_RTC_INST 0x0500
19 #define AM43XX_PRM_TAMPER_INST 0x0600
20 #define AM43XX_PRM_CEFUSE_INST 0x0700
21 #define AM43XX_PRM_PER_INST 0x0800
22 #define AM43XX_PRM_WKUP_INST 0x2000
23 #define AM43XX_PRM_DEVICE_INST 0x4000
26 #define AM43XX_PRM_IRQSTATUS_MPU_OFFSET 0x0004
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/net/
Dfsl,cpm-enet.yaml52 reg = <0x11300 0x20 0x8400 0x100 0x11390 1>;
57 fsl,cpm-command = <0x12000300>;
/linux-6.14.4/drivers/accel/habanalabs/include/gaudi/asic_reg/
Dgaudi_blocks.h16 #define mmNIC0_PHY0_BASE 0x0ull
17 #define NIC0_PHY0_MAX_OFFSET 0x9F13
18 #define mmMME0_ACC_BASE 0x7FFC020000ull
19 #define MME0_ACC_MAX_OFFSET 0x5C00
20 #define MME0_ACC_SECTION 0x20000
21 #define mmMME0_SBAB_BASE 0x7FFC040000ull
22 #define MME0_SBAB_MAX_OFFSET 0x5800
23 #define MME0_SBAB_SECTION 0x1000
24 #define mmMME0_PRTN_BASE 0x7FFC041000ull
25 #define MME0_PRTN_MAX_OFFSET 0x5000
[all …]
/linux-6.14.4/arch/m68k/include/asm/
Dapollohw.h52 #define IO_BASE 0x80000000
62 #define SAU7_SIO01_PHYSADDR 0x10400
63 #define SAU7_SIO23_PHYSADDR 0x10500
64 #define SAU7_RTC_PHYSADDR 0x10900
65 #define SAU7_PICA 0x11000
66 #define SAU7_PICB 0x11100
67 #define SAU7_CPUCTRL 0x10100
68 #define SAU7_TIMER 0x010800
70 #define SAU8_SIO01_PHYSADDR 0x8400
71 #define SAU8_RTC_PHYSADDR 0x8900
[all …]
Dm54xxpci.h21 #define PCIIDR (CONFIG_MBAR + 0xb00) /* PCI device/vendor ID */
22 #define PCISCR (CONFIG_MBAR + 0xb04) /* PCI status/command */
23 #define PCICCRIR (CONFIG_MBAR + 0xb08) /* PCI class/revision */
24 #define PCICR1 (CONFIG_MBAR + 0xb0c) /* PCI configuration 1 */
25 #define PCIBAR0 (CONFIG_MBAR + 0xb10) /* PCI base address 0 */
26 #define PCIBAR1 (CONFIG_MBAR + 0xb14) /* PCI base address 1 */
27 #define PCICCPR (CONFIG_MBAR + 0xb28) /* PCI cardbus CIS pointer */
28 #define PCISID (CONFIG_MBAR + 0xb2c) /* PCI subsystem IDs */
29 #define PCIERBAR (CONFIG_MBAR + 0xb30) /* PCI expansion ROM */
30 #define PCICPR (CONFIG_MBAR + 0xb34) /* PCI capabilities pointer */
[all …]
/linux-6.14.4/include/video/
Dtrident.h4 #define TRIDENTFB_DEBUG 0
20 #define CYBER9320 0x9320
21 #define CYBER9388 0x9388
22 #define CYBER9382 0x9382 /* the real PCI id for this is 9660 */
23 #define CYBER9385 0x9385 /* ditto */
24 #define CYBER9397 0x9397
25 #define CYBER9397DVD 0x939A
26 #define CYBER9520 0x9520
27 #define CYBER9525DVD 0x9525
28 #define TGUI9440 0x9440
[all …]
/linux-6.14.4/tools/perf/tests/shell/attr/
Dtest-stat-default33 type=0
34 config=0
40 type=0
46 type=0
53 type=0
60 type=0
67 type=0
71 # PERF_TYPE_RAW / slots (0x400)
80 # PERF_TYPE_RAW / topdown-retiring (0x8000)
86 disabled=0
[all …]
Dtest-stat-detailed-134 type=0
35 config=0
41 type=0
48 type=0
55 type=0
62 type=0
69 type=0
73 # PERF_TYPE_RAW / slots (0x400)
82 # PERF_TYPE_RAW / topdown-retiring (0x8000)
88 disabled=0
[all …]
Dtest-stat-detailed-234 type=0
35 config=0
41 type=0
48 type=0
55 type=0
62 type=0
69 type=0
73 # PERF_TYPE_RAW / slots (0x400)
82 # PERF_TYPE_RAW / topdown-retiring (0x8000)
88 disabled=0
[all …]
Dtest-stat-detailed-334 type=0
35 config=0
41 type=0
48 type=0
55 type=0
62 type=0
69 type=0
73 # PERF_TYPE_RAW / slots (0x400)
82 # PERF_TYPE_RAW / topdown-retiring (0x8000)
88 disabled=0
[all …]
/linux-6.14.4/arch/powerpc/boot/dts/
Dep8248e.dts26 #size-cells = <0>;
28 PowerPC,8248@0 {
30 reg = <0>;
35 timebase-frequency = <0>;
36 clock-frequency = <0>;
46 reg = <0xf0010100 0x40>;
48 ranges = <0 0 0xfc000000 0x04000000
49 1 0 0xfa000000 0x00008000>;
51 flash@0,3800000 {
53 reg = <0 0x3800000 0x800000>;
[all …]
Dmgcoge.dts23 #size-cells = <0>;
25 PowerPC,8247@0 {
27 reg = <0>;
32 timebase-frequency = <0>; /* Filled in by U-Boot */
33 clock-frequency = <0>; /* Filled in by U-Boot */
34 bus-frequency = <0>; /* Filled in by U-Boot */
44 reg = <0xf0010100 0x40>;
46 ranges = <0 0 0xfe000000 0x00400000
47 1 0 0x30000000 0x00010000
48 2 0 0x40000000 0x00010000
[all …]
/linux-6.14.4/drivers/net/usb/
Dsr9800.h16 #define SR_CMD_SET_SW_MII 0x06
18 #define SR_CMD_READ_MII_REG 0x07
20 #define SR_CMD_WRITE_MII_REG 0x08
22 #define SR_CMD_SET_HW_MII 0x0a
24 #define SR_CMD_READ_EEPROM 0x0b
26 #define SR_CMD_WRITE_EEPROM 0x0c
28 #define SR_CMD_WRITE_ENABLE 0x0d
30 #define SR_CMD_WRITE_DISABLE 0x0e
32 #define SR_CMD_READ_RX_CTL 0x0f
33 #define SR_RX_CTL_PRO (1 << 0)
[all …]
/linux-6.14.4/drivers/net/phy/
Dbcm-cygnus.c18 #define MII_BCM_CYGNUS_AFE_VDAC_ICTRL_0 0x91E5 /* VDAL Control register */
25 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, 0x0c30); in bcm_cygnus_afe_config()
26 if (rc < 0) in bcm_cygnus_afe_config()
30 rc = bcm_phy_write_misc(phydev, 0x39, 0x01, 0xA7C8); in bcm_cygnus_afe_config()
31 if (rc < 0) in bcm_cygnus_afe_config()
35 rc = bcm_phy_write_misc(phydev, 0x3A, 0x00, 0x0803); in bcm_cygnus_afe_config()
36 if (rc < 0) in bcm_cygnus_afe_config()
40 rc = bcm_phy_write_misc(phydev, 0x3A, 0x01, 0xA740); in bcm_cygnus_afe_config()
41 if (rc < 0) in bcm_cygnus_afe_config()
45 rc = bcm_phy_write_misc(phydev, 0x3A, 0x03, 0x8400); in bcm_cygnus_afe_config()
[all …]
/linux-6.14.4/drivers/media/dvb-frontends/
Dmxl5xx_regs.h13 #define HYDRA_INTR_STATUS_REG 0x80030008
14 #define HYDRA_INTR_MASK_REG 0x8003000C
16 #define HYDRA_CRYSTAL_SETTING 0x3FFFC5F0 /* 0 - 24 MHz & 1 - 27 MHz */
17 #define HYDRA_CRYSTAL_CAP 0x3FFFEDA4 /* 0 - 24 MHz & 1 - 27 MHz */
19 #define HYDRA_CPU_RESET_REG 0x8003003C
20 #define HYDRA_CPU_RESET_DATA 0x00000400
22 #define HYDRA_RESET_TRANSPORT_FIFO_REG 0x80030028
23 #define HYDRA_RESET_TRANSPORT_FIFO_DATA 0x00000000
25 #define HYDRA_RESET_BBAND_REG 0x80030024
26 #define HYDRA_RESET_BBAND_DATA 0x00000000
[all …]
/linux-6.14.4/drivers/video/fbdev/geode/
Ddisplay_gx1.c30 outb(CONFIG_CCR3, 0x22); in gx1_read_conf_reg()
31 ccr3 = inb(0x23); in gx1_read_conf_reg()
32 outb(CONFIG_CCR3, 0x22); in gx1_read_conf_reg()
33 outb(ccr3 | CONFIG_CCR3_MAPEN, 0x23); in gx1_read_conf_reg()
34 outb(reg, 0x22); in gx1_read_conf_reg()
35 val = inb(0x23); in gx1_read_conf_reg()
36 outb(CONFIG_CCR3, 0x22); in gx1_read_conf_reg()
37 outb(ccr3, 0x23); in gx1_read_conf_reg()
46 return (gx1_read_conf_reg(CONFIG_GCR) & 0x03) << 30; in gx1_gx_base()
54 unsigned dram_size = 0, fb_base; in gx1_frame_buffer_size()
[all …]
/linux-6.14.4/sound/soc/codecs/
Drt711-sdca.c37 if (ret < 0) in rt711_sdca_index_write()
53 if (ret < 0) in rt711_sdca_index_read()
68 if (ret < 0) in rt711_sdca_index_update_bits()
81 RT711_HDA_LEGACY_RESET_CTL, 0x1, 0x1); in rt711_sdca_reset()
87 case 0x00: in rt711_sdca_ge_force_jack_type()
88 rt711_sdca_index_update_bits(rt711, RT711_VENDOR_REG, RT711_COMBO_JACK_AUTO_CTL1, 0x8400, 0x0000); in rt711_sdca_ge_force_jack_type()
89 rt711_sdca_index_update_bits(rt711, RT711_VENDOR_HDA_CTL, RT711_PUSH_BTN_INT_CTL0, 0x10, 0x00); in rt711_sdca_ge_force_jack_type()
91 case 0x03: in rt711_sdca_ge_force_jack_type()
92 rt711_sdca_index_update_bits(rt711, RT711_VENDOR_REG, RT711_COMBO_JACK_AUTO_CTL1, 0x8400, 0x8000); in rt711_sdca_ge_force_jack_type()
93 rt711_sdca_index_update_bits(rt711, RT711_VENDOR_HDA_CTL, RT711_PUSH_BTN_INT_CTL0, 0x17, 0x13); in rt711_sdca_ge_force_jack_type()
[all …]
/linux-6.14.4/include/media/
Ddvb-usb-ids.h23 #define USB_VID_774 0x7a69
24 #define USB_VID_ADSTECH 0x06e1
25 #define USB_VID_AFATECH 0x15a4
26 #define USB_VID_ALCOR_MICRO 0x058f
27 #define USB_VID_ALINK 0x05e3
28 #define USB_VID_AME 0x06be
29 #define USB_VID_AMT 0x1c73
30 #define USB_VID_ANCHOR 0x0547
31 #define USB_VID_ANSONIC 0x10b9
32 #define USB_VID_ANUBIS_ELECTRONIC 0x10fd
[all …]
/linux-6.14.4/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-tegra.c32 #define XPCS_WRAP_UPHY_RX_CONTROL 0x801c
40 #define XPCS_WRAP_UPHY_RX_CONTROL_RX_DATA_EN BIT(0)
41 #define XPCS_WRAP_UPHY_HW_INIT_CTRL 0x8020
42 #define XPCS_WRAP_UPHY_HW_INIT_CTRL_TX_EN BIT(0)
44 #define XPCS_WRAP_UPHY_STATUS 0x8044
45 #define XPCS_WRAP_UPHY_STATUS_TX_P_UP BIT(0)
46 #define XPCS_WRAP_IRQ_STATUS 0x8050
50 #define XPCS_REG_ADDR_MASK 0x1fff
51 #define XPCS_ADDR 0x3fc
53 #define MGBE_WRAP_COMMON_INTR_ENABLE 0x8704
[all …]
/linux-6.14.4/arch/arm/boot/dts/ti/omap/
Dam43xx-clocks.dtsi9 #clock-cells = <0>;
14 reg = <0x0040>;
18 #clock-cells = <0>;
23 reg = <0x0040>;
27 #clock-cells = <0>;
32 reg = <0x0040>;
36 #clock-cells = <0>;
45 #clock-cells = <0>;
54 #clock-cells = <0>;
63 #clock-cells = <0>;
[all …]
/linux-6.14.4/include/linux/mfd/mt6332/
Dregisters.h10 #define MT6332_HWCID 0x8000
11 #define MT6332_SWCID 0x8002
12 #define MT6332_TOP_CON 0x8004
13 #define MT6332_DDR_VREF_AP_CON 0x8006
14 #define MT6332_DDR_VREF_DQ_CON 0x8008
15 #define MT6332_DDR_VREF_CA_CON 0x800A
16 #define MT6332_TEST_OUT 0x800C
17 #define MT6332_TEST_CON0 0x800E
18 #define MT6332_TEST_CON1 0x8010
19 #define MT6332_TESTMODE_SW 0x8012
[all …]
/linux-6.14.4/arch/mips/include/asm/
Dcpu.h16 register 15, select 0) is defined in this (backwards compatible) way:
24 that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
28 #define PRID_OPT_MASK 0xff000000
34 #define PRID_COMP_MASK 0xff0000
36 #define PRID_COMP_LEGACY 0x000000
37 #define PRID_COMP_MIPS 0x010000
38 #define PRID_COMP_BROADCOM 0x020000
39 #define PRID_COMP_ALCHEMY 0x030000
40 #define PRID_COMP_SIBYTE 0x040000
41 #define PRID_COMP_SANDCRAFT 0x050000
[all …]
/linux-6.14.4/drivers/clk/imx/
Dclk-imx93.c20 #define PLAT_IMX93 BIT(0)
65 { IMX93_CLK_A55_PERIPH, "a55_periph_root", 0x0000, FAST_SEL, CLK_IS_CRITICAL },
66 { IMX93_CLK_A55_MTR_BUS, "a55_mtr_bus_root", 0x0080, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL },
67 { IMX93_CLK_A55, "a55_alt_root", 0x0100, FAST_SEL, CLK_IS_CRITICAL },
68 { IMX93_CLK_M33, "m33_root", 0x0180, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL },
69 { IMX93_CLK_BUS_WAKEUP, "bus_wakeup_root", 0x0280, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL },
70 { IMX93_CLK_BUS_AON, "bus_aon_root", 0x0300, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL },
71 { IMX93_CLK_WAKEUP_AXI, "wakeup_axi_root", 0x0380, FAST_SEL, CLK_IS_CRITICAL },
72 { IMX93_CLK_SWO_TRACE, "swo_trace_root", 0x0400, LOW_SPEED_IO_SEL, },
73 { IMX93_CLK_M33_SYSTICK, "m33_systick_root", 0x0480, LOW_SPEED_IO_SEL, 0, PLAT_IMX93, },
[all …]

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