32 #define XPCS_WRAP_UPHY_RX_CONTROL 0x801c
40 #define XPCS_WRAP_UPHY_RX_CONTROL_RX_DATA_EN BIT(0)
41 #define XPCS_WRAP_UPHY_HW_INIT_CTRL 0x8020
42 #define XPCS_WRAP_UPHY_HW_INIT_CTRL_TX_EN BIT(0)
44 #define XPCS_WRAP_UPHY_STATUS 0x8044
45 #define XPCS_WRAP_UPHY_STATUS_TX_P_UP BIT(0)
46 #define XPCS_WRAP_IRQ_STATUS 0x8050
50 #define XPCS_REG_ADDR_MASK 0x1fff
51 #define XPCS_ADDR 0x3fc
53 #define MGBE_WRAP_COMMON_INTR_ENABLE	0x8704
55 #define MGBE_WRAP_AXI_ASID0_CTRL	0x8400
78 	if (err < 0)  in tegra_mgbe_resume()
82 	if (err < 0)  in tegra_mgbe_resume()
92 	if ((value & XPCS_WRAP_UPHY_STATUS_TX_P_UP) == 0) {  in tegra_mgbe_resume()
99 				 (value & XPCS_WRAP_UPHY_HW_INIT_CTRL_TX_EN) == 0,  in tegra_mgbe_resume()
101 	if (err < 0) {  in tegra_mgbe_resume()
108 	if (err < 0)  in tegra_mgbe_resume()
143 				 (value & XPCS_WRAP_UPHY_RX_CONTROL_RX_CAL_EN) == 0,  in mgbe_uphy_lane_bringup_serdes_up()
145 	if (err < 0) {  in mgbe_uphy_lane_bringup_serdes_up()
177 	if (err < 0) {  in mgbe_uphy_lane_bringup_serdes_up()
185 	return 0;  in mgbe_uphy_lane_bringup_serdes_up()
228 	memset(&res, 0, sizeof(res));  in tegra_mgbe_probe()
230 	irq = platform_get_irq(pdev, 0);  in tegra_mgbe_probe()
231 	if (irq < 0)  in tegra_mgbe_probe()
260 	for (i = 0; i <  ARRAY_SIZE(mgbe_clks); i++)  in tegra_mgbe_probe()
264 	if (err < 0)  in tegra_mgbe_probe()
268 	if (err < 0)  in tegra_mgbe_probe()
279 	if (err < 0)  in tegra_mgbe_probe()
285 	if (err < 0)  in tegra_mgbe_probe()
296 	if (err < 0)  in tegra_mgbe_probe()
302 	if (err < 0)  in tegra_mgbe_probe()
331 	if ((value & XPCS_WRAP_UPHY_STATUS_TX_P_UP) == 0) {  in tegra_mgbe_probe()
338 				 (value & XPCS_WRAP_UPHY_HW_INIT_CTRL_TX_EN) == 0,  in tegra_mgbe_probe()
340 	if (err < 0) {  in tegra_mgbe_probe()
362 	if (err < 0)  in tegra_mgbe_probe()
365 	return 0;  in tegra_mgbe_probe()