/linux-6.14.4/arch/powerpc/include/asm/book3s/32/ |
D | mmu-hash.h | 14 #define BL_128K 0x000 15 #define BL_256K 0x001 16 #define BL_512K 0x003 17 #define BL_1M 0x007 18 #define BL_2M 0x00F 19 #define BL_4M 0x01F 20 #define BL_8M 0x03F 21 #define BL_16M 0x07F 22 #define BL_32M 0x0FF 23 #define BL_64M 0x1FF [all …]
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/linux-6.14.4/drivers/accel/habanalabs/include/goya/asic_reg/ |
D | goya_blocks.h | 16 #define mmPCI_NRTR_BASE 0x7FFC000000ull 17 #define PCI_NRTR_MAX_OFFSET 0x608 18 #define PCI_NRTR_SECTION 0x4000 19 #define mmPCI_RD_REGULATOR_BASE 0x7FFC004000ull 20 #define PCI_RD_REGULATOR_MAX_OFFSET 0x74 21 #define PCI_RD_REGULATOR_SECTION 0x1000 22 #define mmPCI_WR_REGULATOR_BASE 0x7FFC005000ull 23 #define PCI_WR_REGULATOR_MAX_OFFSET 0x74 24 #define PCI_WR_REGULATOR_SECTION 0x3B000 25 #define mmMME1_RTR_BASE 0x7FFC040000ull [all …]
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D | pci_nrtr_regs.h | 22 #define mmPCI_NRTR_HBW_MAX_CRED 0x100 24 #define mmPCI_NRTR_LBW_MAX_CRED 0x120 26 #define mmPCI_NRTR_DBG_E_ARB 0x300 28 #define mmPCI_NRTR_DBG_W_ARB 0x304 30 #define mmPCI_NRTR_DBG_N_ARB 0x308 32 #define mmPCI_NRTR_DBG_S_ARB 0x30C 34 #define mmPCI_NRTR_DBG_L_ARB 0x310 36 #define mmPCI_NRTR_DBG_E_ARB_MAX 0x320 38 #define mmPCI_NRTR_DBG_W_ARB_MAX 0x324 40 #define mmPCI_NRTR_DBG_N_ARB_MAX 0x328 [all …]
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/linux-6.14.4/arch/arm64/boot/dts/freescale/ |
D | imx8mn-pinfunc.h | 14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0 15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3 16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0 17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3 18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0 19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0 20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0 21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0 22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0 23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0 [all …]
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D | imx8mm-pinfunc.h | 14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0… 15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0… 16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0… 17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0… 18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0… 19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0… 20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0… 21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0… 22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0… 23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0… [all …]
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D | imx8mp-pinfunc.h | 13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0 14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0 15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0 16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0 17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0 18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0 19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0 20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0 21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0 22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0 [all …]
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D | imx8mq-pinfunc.h | 15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0… 16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0… 17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0… 18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0… 19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0… 20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0… 21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0… 22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0… 23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0… 24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0… [all …]
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/linux-6.14.4/arch/arm64/boot/dts/marvell/ |
D | armada-7040.dtsi | 20 <0x0 &smmu 0x480 0x20>, 21 <0x100 &smmu 0x4a0 0x20>, 22 <0x200 &smmu 0x4c0 0x20>; 23 iommu-map-mask = <0x031f>; 27 iommus = <&smmu 0x444>; 31 iommus = <&smmu 0x445>; 35 iommus = <&smmu 0x440>; 39 iommus = <&smmu 0x441>;
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D | armada-8040.dtsi | 20 <0x0 &smmu 0x480 0x20>, 21 <0x100 &smmu 0x4a0 0x20>, 22 <0x200 &smmu 0x4c0 0x20>; 23 iommu-map-mask = <0x031f>; 36 iommus = <&smmu 0x444>; 40 iommus = <&smmu 0x445>; 44 iommus = <&smmu 0x440>; 48 iommus = <&smmu 0x441>; 52 iommus = <&smmu 0x454>; 56 iommus = <&smmu 0x450>; [all …]
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/linux-6.14.4/drivers/gpu/drm/msm/disp/dpu1/ |
D | dpu_hwio.h | 13 #define DISP_INTF_SEL 0x004 14 #define INTR_EN 0x010 15 #define INTR_STATUS 0x014 16 #define INTR_CLEAR 0x018 17 #define INTR2_EN 0x008 18 #define INTR2_STATUS 0x00c 19 #define SSPP_SPARE 0x028 20 #define INTR2_CLEAR 0x02c 21 #define HIST_INTR_EN 0x01c 22 #define HIST_INTR_STATUS 0x020 [all …]
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/linux-6.14.4/arch/arm/boot/dts/nxp/imx/ |
D | imxrt1170-pinfunc.h | 10 #define IMX_PAD_SION 0x40000000 17 #define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0 18 #define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0 19 #define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0 20 #define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0 21 #define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0 22 #define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0 23 #define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0 24 #define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0 26 #define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0 [all …]
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D | imx6sl-pinfunc.h | 13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0 14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0 15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0 16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0 17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0 18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0 19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0 20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0 21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0 22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0 [all …]
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D | imx6q-pinfunc.h | 13 #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0 14 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0 15 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0 16 #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0 17 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0 18 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0 19 #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0 20 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0 21 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0 22 #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0 [all …]
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D | imx50-pinfunc.h | 13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0 14 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0 15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0 16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0 17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0 18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0 19 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0 20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0 21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0 22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0 [all …]
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D | imx51-pinfunc.h | 13 #define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0 14 #define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0 15 #define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0 16 #define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0 17 #define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0 18 #define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0 19 #define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0 20 #define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0 21 #define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0 22 #define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0 [all …]
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/linux-6.14.4/arch/arm/mach-s5pv210/ |
D | regs-clock.h | 12 #define S3C_ADDR_BASE 0xF6000000 14 #define S3C_VA_SYS S3C_ADDR(0x00100000) 18 #define S5P_APLL_LOCK S5P_CLKREG(0x00) 19 #define S5P_MPLL_LOCK S5P_CLKREG(0x08) 20 #define S5P_EPLL_LOCK S5P_CLKREG(0x10) 21 #define S5P_VPLL_LOCK S5P_CLKREG(0x20) 23 #define S5P_APLL_CON S5P_CLKREG(0x100) 24 #define S5P_MPLL_CON S5P_CLKREG(0x108) 25 #define S5P_EPLL_CON S5P_CLKREG(0x110) 26 #define S5P_EPLL_CON1 S5P_CLKREG(0x114) [all …]
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/linux-6.14.4/Documentation/devicetree/bindings/remoteproc/ |
D | qcom,sc7180-mss-pil.yaml | 198 reg = <0x04080000 0x10000>, <0x04180000 0x48>; 201 iommus = <&apps_smmu 0x461 0x0>, <&apps_smmu 0x444 0x3>; 204 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 231 qcom,smem-states = <&modem_smp2p_out 0>; 238 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; 239 qcom,spare-regs = <&tcsr_regs 0xb3e4>;
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/linux-6.14.4/drivers/net/ethernet/broadcom/asp2/ |
D | bcmasp_intf_defs.h | 6 ((((intf)->port) * 0x800) + 0xc000) 7 #define UMC_CMD 0x008 8 #define UMC_CMD_TX_EN BIT(0) 10 #define UMC_CMD_SPEED_SHIFT 0x2 11 #define UMC_CMD_SPEED_MASK 0x3 12 #define UMC_CMD_SPEED_10 0x0 13 #define UMC_CMD_SPEED_100 0x1 14 #define UMC_CMD_SPEED_1000 0x2 15 #define UMC_CMD_SPEED_2500 0x3 33 #define UMC_MAC0 0x0c [all …]
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/linux-6.14.4/arch/arm/boot/dts/qcom/ |
D | qcom-apq8084.dtsi | 21 reg = <0xfa00000 0x200000>; 28 #size-cells = <0>; 30 cpu@0 { 33 reg = <0>; 94 reg = <0x0 0x0>; 189 interrupts = <GIC_PPI 7 0xf04>; 195 #clock-cells = <0>; 201 #clock-cells = <0>; 208 interrupts = <GIC_PPI 2 0xf08>, 209 <GIC_PPI 3 0xf08>, [all …]
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/linux-6.14.4/drivers/staging/rtl8723bs/hal/ |
D | HalHWImg8723B_MAC.c | 16 ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA */ in CheckPositive() 31 pDM_Odm->TypeGLNA << 0 | in CheckPositive() 40 if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) in CheckPositive() 42 if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) in CheckPositive() 48 cond1 &= 0x000F0FFF; in CheckPositive() 49 driver1 &= 0x000F0FFF; in CheckPositive() 52 u32 bitMask = 0; in CheckPositive() 53 if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE */ in CheckPositive() 56 if ((cond1 & BIT0) != 0) /* GLNA */ in CheckPositive() 57 bitMask |= 0x000000FF; in CheckPositive() [all …]
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/linux-6.14.4/drivers/gpu/drm/renesas/shmobile/ |
D | shmob_drm_regs.h | 19 #define LDDCKPAT1R 0x400 20 #define LDDCKPAT2R 0x404 21 #define LDDCKR 0x410 22 #define LDDCKR_ICKSEL_BUS (0 << 16) 28 #define LDDCKSTPR 0x414 30 #define LDDCKSTPR_DCKSTP (1 << 0) 31 #define LDMT1R 0x418 40 #define LDMT1R_MIFTYP_RGB8 (0x0 << 0) 41 #define LDMT1R_MIFTYP_RGB9 (0x4 << 0) 42 #define LDMT1R_MIFTYP_RGB12A (0x5 << 0) [all …]
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/linux-6.14.4/drivers/media/pci/cx18/ |
D | cx18-av-core.h | 32 CX18_AV_SVIDEO_LUMA1 = 0x10, 33 CX18_AV_SVIDEO_LUMA2 = 0x20, 34 CX18_AV_SVIDEO_LUMA3 = 0x30, 35 CX18_AV_SVIDEO_LUMA4 = 0x40, 36 CX18_AV_SVIDEO_LUMA5 = 0x50, 37 CX18_AV_SVIDEO_LUMA6 = 0x60, 38 CX18_AV_SVIDEO_LUMA7 = 0x70, 39 CX18_AV_SVIDEO_LUMA8 = 0x80, 40 CX18_AV_SVIDEO_CHROMA4 = 0x400, 41 CX18_AV_SVIDEO_CHROMA5 = 0x500, [all …]
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/linux-6.14.4/arch/powerpc/platforms/cell/ |
D | spider-pic.c | 23 TIR_DEN = 0x004, /* Detection Enable Register */ 24 TIR_MSK = 0x084, /* Mask Level Register */ 25 TIR_EDC = 0x0c0, /* Edge Detection Clear Register */ 26 TIR_PNDA = 0x100, /* Pending Register A */ 27 TIR_PNDB = 0x104, /* Pending Register B */ 28 TIR_CS = 0x144, /* Current Status Register */ 29 TIR_LCSA = 0x150, /* Level Current Status Register A */ 30 TIR_LCSB = 0x154, /* Level Current Status Register B */ 31 TIR_LCSC = 0x158, /* Level Current Status Register C */ 32 TIR_LCSD = 0x15c, /* Level Current Status Register D */ [all …]
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/linux-6.14.4/drivers/net/ethernet/freescale/enetc/ |
D | netc_blk_ctrl.c | 30 #define IMX95_CFG_LINK_IO_VAR 0x0 31 #define IO_VAR_16FF_16G_SERDES 0x1 32 #define IO_VAR(port, var) (((var) & 0xf) << ((port) << 2)) 34 #define IMX95_CFG_LINK_MII_PROT 0x4 35 #define CFG_LINK_MII_PORT_0 GENMASK(3, 0) 37 #define MII_PROT_MII 0x0 38 #define MII_PROT_RMII 0x1 39 #define MII_PROT_RGMII 0x2 40 #define MII_PROT_SERIAL 0x3 41 #define MII_PROT(port, prot) (((prot) & 0xf) << ((port) << 2)) [all …]
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/linux-6.14.4/drivers/usb/serial/ |
D | xr_serial.c | 34 #define XR21V141X_UART_REG_BLOCK 0 36 #define XR21V141X_UART_CUSTOM_BLOCK 0x66 39 #define XR21V141X_CLOCK_DIVISOR_0 0x04 40 #define XR21V141X_CLOCK_DIVISOR_1 0x05 41 #define XR21V141X_CLOCK_DIVISOR_2 0x06 42 #define XR21V141X_TX_CLOCK_MASK_0 0x07 43 #define XR21V141X_TX_CLOCK_MASK_1 0x08 44 #define XR21V141X_RX_CLOCK_MASK_0 0x09 45 #define XR21V141X_RX_CLOCK_MASK_1 0x0a 46 #define XR21V141X_REG_FORMAT 0x0b [all …]
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